ZIOL2201 datasheet(54/92 Pages) RENESAS

54 / 92 page

ZIOL2xxx Datasheet

April 26, 2016

“sense” resistors which are interconnected to the L+ and L- pin of the sensor/actuator device. Those resistors

provide a voltage divider. The so downscaled supply voltage (voltage at the pin PFD) is compared with the output

voltage of an IC-internal voltage divider. In case of abnormal power supply of the IC (refer to Figure 3.20) a

window comparator will detect this situation as LINE_FAULT event. The further processing of the LINE_FAULT

event depends on the LF_ENABLE configuration flag (Figure 3.20). A Power-Fail Lock (LOCK_PF) will be

generated only if the duration of the so detected abnormal power supply (or break of power supply) is longer than

10ms (Figure 3.20).

3.5.3.

Under-voltage Detector

The IC has a Power-on-reset circuit which puts the IC in RESET state while power-on, or if the internal (core)

supply voltage of 3.3V (voltage at LR_OUT) drops below a critical value. For example with VDD = 5V the internal

3.3V power supply may not be jeopardized thus the IC control will work as usual. In this situation the under-

voltage detection shall protect the HV driver which may not work correctly with VDD < 8V and which might have a

chance to get damaged in this situation. If configured the Under-Voltage detector will avoid this situation by

locking both driver channels.

3.5.4.

Channel Locking and Interrupt Generation

As mentioned in chapter 3.5.1 both channels can be locked if one or both of the events LINE_FAULT and

UNDER_VOLTAGE occur. In this case the resulting signal LOCK_PF (refer to Figure 3.20) will be stored in the

IRQ_STATUS status register [18][7] (refer to Table 3.7). Depending on the IRQ_ENABLE configuration register

[0][7] or on IRQ_NOREG (configuration register [14][3]) and interrupt (pin INT_L ) can be issued.

3.5.5.

Downward Compatibility

The introduction of the PFD in IC Rev B goes in parallel with the conversion of the formerly master enable (M_EN)

pin to a voltage sense pin (PFD pin). Therefore the master enable /disable function must be defined by using a

configuration flag. Since old PCB designs are using the M_EN interconnection either to VDD/LR_OUT or VSS

(enabling/disabling the master functionality), the LF feature cannot be used.

3.6.

DC/DC Converter

3.6.1.

Principle of Operation

The on chip DC/DC converter is a constant frequency (2.5MHz) buck converter with an adjustable output voltage.

The wide input voltage range of 8V to 36V, a minimized output ripple (< 25mVpp), and the maximum output

current of 50mA make the converter suitable for standard sensor/actuator applications. The output voltage can be

adjusted with an external voltage divider.

The electrical characteristics are shown in the chapter “operating conditions” (chapter 1).

The DC/DC converter can be disabled if the application does not require this functionality. In order to do this the

FB pin shall be connected to the 3.3V LV power supply output (pin LR_OUT).

1 Only available with IC versions ZIOL240x/220x/210x

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