ZIOL2201 datasheet(30/92 Pages) RENESAS

30 / 92 page

ZIOL2xxx Datasheet

April 26, 2016

Figure 3.10 General timing of a byte transfer

TX_EN / SPI_CLK

SPI_EN_L

MOSI

MISO

MOSI sampling

COM channel state defined

by TX_EN, TX, RX

SPI operation starts here, COM

channel state is „latched“ with the

SPI_EN_L HL transition

SPI operation ends

here, COM channel

state defined by

TX_EN, TX, RX

SPI feature summary:

• The interface works in SPI-slave mode only

• The timing follows the scheme in Figure 3.10 which defines

▬ Clock Polarity CPOL = 1 (clock is idle high)

▬ Clock Phase CPHA = 1 (data captured with 2nd clock edge after SPI_EN_L went low; data are read on

clock’s rising edge and data are changed on a falling edge)

• Maximum clock frequency of the SPI_CLK shall not exceed 4 MHz for accessing the on-chip EEPROM and

10 MHz for other SPI accesses

• SPI clock duty cycle: 40…60%

• MSB will be transmitted first

• If access exceeds last byte, a wrap will NOT happen – the last byte will be written correctly, rest will be

disregarded

• Block write (access to more than one address location) is only supported for the configuration-register area

but not for the EEPROM area.

• Block read is supported for both the EEPROM and configuration-register area.

• During enabling the SPI (SPI_EN_L = low ) the input lines of the COM driver are latched, so the COM

driver does not change its output state while SPI is enabled.

The SPI telegram structure can be divided into three types of SPI accesses:

• READ: read access to register file or EEPROM, block access possible

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