ZIOL2201 datasheet(3/92 Pages) RENESAS

3 / 92 page

ZIOL2xxx Datasheet

April 26, 2016

List of Figures

Figure 2.1

Max. Total Power Dissipation ................................................................................................................6

Figure 2.2

Efficiency of the DC/DC converter for VOUT=5V, C=10µF and L=10µH ............................................12

Figure 3.1

Functional Block Diagram of the ZIOL2xxx .........................................................................................13

Figure 3.2

ZIOL24xx Transceiver Data Path in Principle......................................................................................14

Figure 3.3

ZIOL22xx Transceiver Data Path in Principle......................................................................................15

Figure 3.4

ZIOL21xx Transceiver Data Path in Principle......................................................................................16

Figure 3.5

ZIOL24xx in Device and Master Mode Application..............................................................................19

Figure 3.6

Typical IO-Link Device Configuration with HS driver only ...................................................................22

Figure 3.7

Wake-Up Signal Recognition...............................................................................................................24

Figure 3.8

The Basic Scheme of the IC Self Protection .......................................................................................26

Figure 3.9

Memory Unit.........................................................................................................................................28

Figure 3.10 General timing of a byte transfer .........................................................................................................30

Figure 3.11 Structure of SPI accesses ...................................................................................................................31

Figure 3.12 SPI Command Structure ......................................................................................................................32

Figure 3.13 SPI Timing ...........................................................................................................................................34

Figure 3.14 Interrupt (INT_L pin) and Wake-up (WURQ_L pin) Signaling .............................................................45

Figure 3.15 COM Channel Lock Control .................................................................................................................46

Figure 3.16 AUX Channel Lock Control ..................................................................................................................47

Figure 3.17 Over-Temperature Lock Control ..........................................................................................................48

Figure 3.18 Internal IC Sensors and related Overload and Over-Temperature Detection Circuits ........................50

Figure 3.19 Low Voltage Supply Concept...............................................................................................................52

Figure 3.20 PFD Working Principle.........................................................................................................................53

Figure 3.21 DC/DC Converter in Principle ..............................................................................................................55

Figure 3.22 DC/DC Converter Output Voltage as Function of R1 (R2 = 10kOhms) ..............................................57

Figure 3.23 High frequency critical loops of DC/DC converter for PCB layout .......................................................58

Figure 3.24 PCB layout of Evaluation board as an example ..................................................................................59

Figure 4.1

Simplified Application Circuit with the ZIOL2xxx in Device Mode .......................................................60

Figure 4.2

Simplified Application Circuit with the ZIOL2xxx in Master Mode .......................................................61

Figure 4.3

Power Line Fail Detection ....................................................................................................................62

Figure 4.4

PCB Layout Recommendations...........................................................................................................63

Figure 6.1

Pin Diagram of the ZIOL2xxx...............................................................................................................68

Figure 6.2

Package Dimensions ...........................................................................................................................69

Figure 6.3

Top Marking of the ZIOL2xxx ..............................................................................................................70

Figure 6.4

Package Dimensions ...........................................................................................................................72

Figure 6.5

Package Dimensions WL-CSP ............................................................................................................73

Figure 6.6

Top Marking of the ZIOL2xxx CSP ......................................................................................................74

Figure 9.1

Register Representation in Principle (Example) ..................................................................................78

Figure 10.1 Peak Register Access Scenarios.........................................................................................................82

Figure 10.2 Overload Counter Behavior in permanent Over-Current Situations ....................................................83

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