MFRC522 datasheet(16/109 Pages) NXP

16 / 109 page

112132

Product data sheet

Rev. 3.2 — 22 May 2007

16 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

9.2.1.4

DivIEnReg

Control bits to enable and disable the passing of interrupt requests.

9.2.1.5

CommIRqReg

Contains Interrupt Request bits.

Table 13:

DivIEnReg register (address 03h); reset value: 00h

Bit

Symbol

IRQPushPull

MfinActIEn

CRCIEn

Access

Rights

r/w

RFU

r/w

RFU

r/w

RFU

Table 14:

Description of DivIEnReg bits

Bit

Symbol

Description

IRQPushPull

Set to logic 1, the pin IRQ works as standard CMOS output pad.

Set to logic 0, the pin IRQ works as open drain output pad.

6 to 5

Reserved for future use.

MfinActIEn

Allows the MFIN active interrupt request to be propagated to pin IRQ.

Reserved for future use.

CRCIEn

Allows the CRC interrupt request (indicated by bit CRCIRq) to be

propagated to pin IRQ.

1 to 0

Reserved for future use.

Table 15:

CommIRqReg register (address 04h); reset value: 14h

Bit

Symbol

Set1

TxIRq

RxIRq

IdleIRq

HiAlertIRq

LoAlertIRq

ErrIRq

TimerIRq

Access

Rights

wdy

Table 16:

Description of CommIRqReg bits

All bits in the register CommIRqReg shall be cleared by software.

Bit

Symbol

Description

Set1

Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg

are set.

Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg

are cleared.

TxIRq

Set to logic 1 immediately after the last bit of the transmitted data was sent out.

RxIRq

Set to logic 1 when the receiver detects the end of a valid data stream.

If the bit RxNoErr in register RxModeReg is set to logic 1, Bit RxIRq is only set

to logic 1 when data bytes are available in the FIFO.

IdleIRq

Set to logic 1, when a command terminates by itself e.g. when the

CommandReg changes its value from any command to the Idle Command.

If an unknown command is started, the CommandReg changes its content to

the idle state and the bit IdleIRq is set. Starting the Idle Command by the

μ-Controller does not set bit IdleIRq.

HiAlertIRq

Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to

HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit

Set1.

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