MFRC522 datasheet(65/109 Pages) NXP

65 / 109 page

112132

Product data sheet

Rev. 3.2 — 22 May 2007

65 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

12. FIFO Buffer

12.1 Overview

An 64

× 8-bit FIFO buffer is implemented in the MFRC522. It buffers the input and output

data stream between the host and the internal state machine of the MFRC522. Thus, it is

possible to handle data streams with lengths of up to 64 bytes without taking timing

constraints into account.

12.2 Accessing the FIFO Buffer

The FIFO-buffer input and output data bus is connected to the register FIFODataReg.

Writing to this register stores one byte in the FIFO-buffer and increments the internal

FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents

stored at the FIFO-buffer read-pointer and decrements the FIFO-buffer read-pointer. The

distance between the write- and read-pointer can be obtained by reading the register

FIFOLevelReg.

When the

μ-Controller starts a command, the MFRC522 may, while the command is in

progress, access the FIFO-buffer according to that command. Physically only one

FIFO-buffer is implemented, which can be used in input- and output direction. Therefore

the

μ-Controller has to take care, not to access the FIFO-buffer in an unintended way.

12.3 Controlling the FIFO-Buffer

Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be

reset by setting the bit FlushBuffer in the register FIFOLevelReg to 1. Consequently, the

FIFOLevel bits are set to logic 0, the bit BufferOvfl in the register ErrorReg is cleared, the

actually stored bytes are not accessible any more and the FIFO-buffer can be filled with

another 64 bytes again.

12.4 Status Information about the FIFO-Buffer

The host may obtain the following data about the FIFO-buffers status:

• Number of bytes already stored in the FIFO-buffer: FIFOLevel in register

FIFOLevelReg

• Warning, that the FIFO-buffer is almost full: HiAlert in register Status1Reg

• Warning, that the FIFO-buffer is almost empty: LoAlert in register Status1Reg

• Indication, that bytes were written to the FIFO-buffer although it was already full:

BufferOvfl in register ErrorReg. BufferOvfl can be cleared only by setting bit

FlushBuffer in the register FIFOLevelReg.

The MFRC522 can generate an interrupt signal

• If LoAlertIEn in register CommIEnReg is set to logic 1 it will activate pin IRQ when

LoAlert in the register Status1Reg changes to 1.

• If HiAlertIEN in register CommIEnReg is set to logic 1 it will activate pin IRQ when

HiAlert in the register Status1Reg changes to 1.

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