MFRC522 datasheet(68/109 Pages) NXP

68 / 109 page

112132

Product data sheet

Rev. 3.2 — 22 May 2007

68 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

14. Interrupt Request System

The MFRC522 indicates certain events by setting bit IRq in the register Status1Reg and

additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the

host using its interrupt handling capabilities. This allows the implementation of efficient

host software.

The following table shows the available interrupt bits, the corresponding source and the

condition for its activation. The interrupt bit TimerIRq in register CommIRqReg indicates

an interrupt set by the timer unit. The setting is done when the timer decrements from 1

down to 0.

The TxIRq bit in register CommIRqReg indicates that the transmitter has finished. If the

state changes from sending data to transmitting the end of the frame pattern, the

transmitter unit sets the interrupt bit automatically. The CRC coprocessor sets the bit

CRCIRq in the register DivIRqReg after having processed all data from the FIFO buffer.

This is indicated by the bit CRCReady = 1.

The bit RxIRq in register CommIRqReg indicates an interrupt when the end of the

received data is detected.

The bit IdleIRq in register CommIRqReg is set if a command finishes and the content of

the command register changes to idle.

The bit HiAlertIRq in register CommIRqReg is set to logic 1 if the HiAlert bit is set to

logic 1, that means the FIFO buffer has reached the level indicated by the bit WaterLevel.

The bit LoAlertIRq in register CommIRqReg is set to logic 1 if the LoAlert bit is set to

logic 1, that means the FIFO buffer has reached the level indicated by the bit WaterLevel.

The bit ErrIRq in register CommIRqReg indicates an error detected by the contactless

UART during sending or receiving. This is indicated by any bit set to logic 1 in register

ErrorReg.

Table 148: Interrupt Sources

Interrupt bit

Interrupt Source

Is set automatically, when

TimerIRq

Timer Unit

the timer counts from 1 to 0

TxIRq

Transmitter

a transmitted data stream ends

CRCIRq

CRC co-processor

all data from the FIFO buffer has been processed

RxIRq

Receiver

a received data stream ends

IdleIRq

Command Register

a command execution finishes

HiAlertIRq

FIFO-buffer

the FIFO-buffer is getting full

LoAlertIRq

FIFO-buffer

the FIFO-buffer is getting empty

ErrIRq

contactless UART

an error is detected

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