MFRC522 datasheet(14/109 Pages) NXP

14 / 109 page

112132

Product data sheet

Rev. 3.2 — 22 May 2007

14 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

9.2.1.3

CommIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 9:

CommandReg register (address 01h); reset value: 20h

Bit

Symbol

RcvOff

Power Down

Command

Access

Rights

RFU

r/w

Table 10:

Description of CommandReg bits

Bit

Symbol

Description

7 to 6

Reserved for future use.

RcvOff

Set to logic 1, the analog part of the receiver is switched off.

PowerDown

Set to logic 1, Soft Power-down mode is entered.

Set to logic 0, the MFRC522 starts the wake up procedure. During this

procedure this bit still shows a logic 1. A logic 0 indicates that the

MFRC522 is ready for operations; see Section 16.2 “Soft

Power-down”.

Remark: The bit PowerDown cannot be set, when the command

SoftReset has been activated.

3 to 0

Command

Activates a command according to the Command Code. Reading this

“MFRC522 Commands Overview”).

Table 11:

CommIEnReg register (address 02h); reset value: 80h

Bit

Symbol

IRqInv

TxIEn

RxIEn

IdleIEn

HiAlertIEn

LoAlertIEn

ErrIEn

TimerIEn

Access

Rights

r/w

Table 12:

Description of CommIEnReg bits

Bit

Symbol

Description

IRqInv

Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the

Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with

bit IRqPushPull in register DivIEnReg, the default value of logic 1 ensures,

that the output level on pin IRQ is tristate.

TxIEn

Allows the transmitter interrupt request (indicated by bit TxIRq) to be

propagated to pin IRQ.

RxIEn

Allows the receiver interrupt request (indicated by bit RxIRq) to be

propagated to pin IRQ.

IdleIEn

Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to

pin IRQ.

HiAlertIEn

Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be

propagated to pin IRQ.

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