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DAC38RF80IAAV bảng dữ liệu(PDF) 90 Page - Texas Instruments

tên linh kiện DAC38RF80IAAV
Giải thích chi tiết về linh kiện  DAC38RFxx Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
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Trang chủ  https://www.ti.com
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DAC38RF80IAAV bảng dữ liệu(HTML) 90 Page - Texas Instruments

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7.5.15 JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
Figure 7-48. JESD FIFO Control Register (JESD_FIFO)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-58. JESD_FIFO Field Descriptions
Bit
Field
Type
Reset
Description
15
FIFO_ZEROS_DATA
R/W
1
When asserted FIFO errors zero the data out of the
JESD block. For test purposes this could be turned off
to allow test patterns in the FIFO.
14:13
NOT USED
R/W
000
Not Used
12
SRDS_FIFO_ALM_CLR
R/W
0
Set to 1 to clear FIFO errors. Must be set to 0 for proper
FIFO operation
11
Not used
R/W
0
Not used
10:8
FIFO_OFFSET
R/W
0000
Used to set the difference between read and write
pointers in the JESD FIFO.
7:1
Reserved
R/W
0
Reserved
0
SPI_TXENABLE
R/W
0
When asserted the internal value of txenable = '1'
7.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
Figure 7-49. Alarm Mask 1 Register (ALM_MASK1)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023
www.ti.com
90
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93



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