DAC38RF80IAAV datasheet(46/160 Pages) TI2

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7.3.7 SYNC Interface

The DAC38RFxx JESD204B interface has two differential SYNC outputs called SYNC0 and SYNC1 to support

one or two links. Alternatively, GPO0 and GPO1 can be used to output SYNC as a single-ended CMOS

level. Each of the differential or CMOS outputs is enabled by a 2-bit register (fields GPO0_SEL, GPO1_SEL,

SYNC0B_SEL, SYNC1B_SEL in register IO_CONFIG 8.5.2), with bit 0 enabling multi-DUC1 SYNC and bit 1

enabling multi-DUC2 SYNC. If both are enabled, the SYNC\ signals are OR’ed.

The SYNC signal can be asserted low by the receiver either to make a synchronization request to initialize/

reinitialize the link or to report an error to the transmitter. Synchronization requests must have a minimum

duration of five frames plus nine octets rounded up to the nearest whole number of frames. To report an error,

the SYNC signal is asserted for exactly two frames. The transmitter interprets any negative edge of its SYNC

input as an error and any SYNC assertion lasting four frames or longer as a synchronization request. See the

following sections in the standard for more details.

• 7.6.3 Errors requiring re-initialization

• 7.6.4 Error reporting through SYNC interface

• 8.4 SYNC signal decoding

7.3.8 Single or Dual Link Configuration

The DAC38RFxx JESD204B interface can be configures with one or two links. The advantage of using two links,

one for each DAC, is that one link can be re-established without affecting the other link and DAC.

The configuration for each mode of operation are:

1. Dual DAC, dual link

a. Program fields OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers

JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data

off of the appropriate SerDes lane.

b. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for

each multi-DUC enable the lanes used.

c. Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) should be ‘0’ (default).

2. Dual DAC, single link

a. Program OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers JESD_CROSSBAR1

(8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off the appropriate

SerDes lane.

b. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for

each multi-DUC enable the lanes used.

c. Set field ONE_LINK_ONLY to ‘1’ to configure TXENABLE output.

3. Single DAC, single link

a. Set Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) to ‘1’ to gate clocks to unused multi-

DUC2 for power savings.

b. ONE_LINK_ONLY bit does not matter in this case.

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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