DAC38RF80IAAV datasheet(5/160 Pages) TI2

5 / 160 page

Pin Functions - DAC38RF83, DAC38RF93, DAC38RF85 (continued)

I/O

DESCRIPTION

NAME

NO.

DACCLK+

A10

Device clock, internal 100 Ω differential termination, self-biased, positive terminal.

DACCLK-

Device clock, internal 100 Ω differential termination, self-biased, negative terminal.

DACCLKSE

A12

Single ended device clock optional input. Can be left floating if not used. internal 50 Ω termination.

DGND

A2, B2, C2, D2, D6, E2,

E7, F2, F6, G2, G7, H6,

J7, K2, L2, L3, L4, L5,

Digital ground.

EXTIO

C10

I/O

Requires a 0.1 μF decoupling capacitor to AGND.

GPI0

Factory use only. User should GND.

GPI1

Factory use only. User should GND.

GPO0

Used for CMOS SYNC0\ signal.

GPO1

Used for CMOS SYNC1\ signal.

IFORCE

Test pin for on chip parametrics. Can be left floating.

RBIAS

Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS

(8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.

RESET

Active low input for chip RESET, which resets all the programming registers to their default state. Internal

pull-up.

RX0+

CML SerDes interface lane 0 input, positive

RX0-

CML SerDes interface lane 0 input, negative

RX1+

CML SerDes interface lane 1 input, positive

RX1-

CML SerDes interface lane 1 input, negative

RX2+

CML SerDes interface lane 2 input, positive

RX2-

CML SerDes interface lane 2 input, negative

RX3+

CML SerDes interface lane 3 input, positive

RX3-

CML SerDes interface lane 3 input, negative

RX4+

CML SerDes interface lane 4 input, positive

RX4-

CML SerDes interface lane 4 input, negative

RX5+

CML SerDes interface lane 5 input, positive

RX5-

CML SerDes interface lane 5 input, negative

RX6+

CML SerDes interface lane 6 input, positive

RX6-

CML SerDes interface lane 6 input, negative

RX7+

CML SerDes interface lane 7 input, positive

RX7-

CML SerDes interface lane 7 input, negative

SCLK

Serial interface clock. Internal pull-down.

SDEN

Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.

SDIO

M10

I/O

Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal

pull-down.

SDO

Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode

(default).

SLEEP

Active high asynchronous hardware power-down input. Internal pull-down.

SYNC0+

Synchronization request to transmitter for JESD204B link 0, LVDS positive output.

SYNC0-

Synchronization request to transmitter for JESD204B link 0, LVDS negative output.

SYNC1+

Synchronization request to transmitter for JESD204B link 1, LVDS positive output.

SYNC1-

Synchronization request to transmitter for JESD204B link 1, LVDS negative output.

SYSREF+

LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This positive/negative

pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization.

SYSREF-

LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+

description)

TCLK

JTAG test clock. Internal pull-down

TDI

JTAG test data in. Internal pull-up

TDO

JTAG test data out. Internal pull-up

www.ti.com

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93

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