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TPS3435CGLEFDDFR bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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TPS3435CGLEFDDFR bảng dữ liệu(HTML) 6 Page - Texas Instruments |
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6 / 39 page ![]() Table 5-1. Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See Section 7.3.4 for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. See Section 7.3.2.1 for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See Section 7.3.3 for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See Section 7.3.4 for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 7.3.2.4 for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 7.3.2.4 for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See Section 7.3.2.2 for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin before the timeout expires in order for RESET / WDO to not assert. See Section 7.3.2 for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See Section 7.3.4 for more details. TPS35-Q1 SLVSGE8B – NOVEMBER 2022 – REVISED AUGUST 2024 www.ti.com 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS35-Q1 |
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