above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from

voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options

offered by the device.

The typical timing behavior for a voltage supervisor and the RESET output is showcased in Figure 7-5. The

voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage

supervisor output is asserted, the watchdog functionality is disabled including WDO assert control. The device

resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed.

VDD

WDI

ttDt

tP-HL

Ignore

ttSDt

ttWDt

ttDt

VPOR

VIT+

VIT-

ttWDt

Ignore

ttWDt

ttSDt

ttSDt

Ignore

tP-WD

WDO

RESET

tSTRT + tD

Devices with only RESET output, the output will be AND

operation of RESET and WDO signals.

Figure 7-5. Voltage Supervisor Timing Diagram

7.3.2 Timeout Watchdog Timer

The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple

pinout options A to D which support multiple features to meet ever expanding needs of various applications.

Make sure a correct pinout is selected to meet the application needs.

The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is

deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.

TPS35-Q1 family offers various startup time delay options to make sure enough time is available for the host to

complete boot operation. Please refer Section 7.3.2.3 for additional details.

The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period.

Refer Section 7.3.2.1 section to arrive at the relevant tWD value needed for application. The timer value is reset

when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not

detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout

D. The RESET or WDO is asserted for time tD . Refer Section 7.3.4 to arrive at the relevant tD value needed for

application.

Figure 7-6 shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog

functionality supports multiple features. Details are available in following sub sections.

TPS35-Q1

SLVSGE8B – NOVEMBER 2022 – REVISED AUGUST 2024

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