The device enters watchdog monitoring phase after the device exits the tSD frame.

Failure to provide one of the exit condition within tSD triggers the watchdog error by asserting the WDO output

pin for tD, this is observed in Figure 7-8. For devices with only RESET output, the RESET pin is asserted.

The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin

combination as described in Section 7.3.2.2 section.

Figure 7-8 shows the operation for tSD time frame.

VDD

WDI

Ignore

ttSDt

ttDt

VPOR

VIT+

ttWDt

ttWDt

ttSDt

Ignore

tSTRT + tD

WDO

RESET

Devices with only RESET output, the output will be AND

operation of RESET and WDO signals.

Figure 7-8. tSD Frame Behavior

7.3.2.4 SET Pin Behavior

The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the

user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET

pin can be used are:

• Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is

operational. Watchdog can be used to wake up the host after long duration to perform the application related

activities before going back to sleep.

• Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not

interrupt the critical task. Change timer to application specified interval after the critical task is complete.

The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value

along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in

the Section 4 section. The SET pin logic level is decoded during the device power up. The SET pin value can

be changed any time during the operation. SETx pin change which leads to change of watchdog timer value

or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when

WDO or RESET output is asserted as well. The updated tWD timer value is going be applied after output is

deasserted and the tSD timer is over or terminated.

For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog

Time Scaling selector in the Section 4 section. Table 7-1 showcases an example of the tWD values for different

SET0 logic levels when using Watchdog Time setting as option D = 10ms.

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TPS35-Q1

SLVSGE8B – NOVEMBER 2022 – REVISED AUGUST 2024

Copyright © 2024 Texas Instruments Incorporated

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Product Folder Links: TPS35-Q1