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L99PM72PXP bảng dữ liệu(PDF) 124 Page - STMicroelectronics |
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L99PM72PXP bảng dữ liệu(HTML) 124 Page - STMicroelectronics |
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124 / 128 page ![]() ST SPI L99PM72PXP 124/128 Doc ID 023553 Rev 3 6.2.27 Status Register 5 Table 145. Status register 5: command and data bytes Command byte 1st data byte 2nd data byte Read/write Address Bit <15:8> Bit <7:0> x x 0 1 0 1 0 1 Data, 8bit Data, 8 bit Table 146. Control register 5, data bytes 1st data byte <15:8> 2nd data byte <7:0> Function Reserved Reserved Group Diagnosis 5 Diagnosis 6 Table 147. Status register 5, bits Bit Name Comment Information storage 15 Reserved Must be kept at default 14 Reserved 13 Reserved 12 FECNT_4 Frame Detect Error Counter This counter is increased by 1 in case a frame was not received/decoded correctly (CRC error, stuff-bit error, form error). The counter is decreased by 1 with every frame which is decoded correctly If FECNT = 31, the next erroneous frame will wake- up the device, set FDERR = 1 and reset FECNTx = 0 Live bit updated after each sent CAN frame 11 FECNT_3 10 FECNT_2 9 FECNT_1 8 FECNT_0 7 OSC_FAIL OSC Failure Flag (used device internally) Bit is latched until a read and clear access 6Reserved Must be kept at default 5Reserved 4 - 0 Osc_mon Monitoring of internal oscillator (used internally) Live bit updated after each sent CAN frame |
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