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L99PM72PXP bảng dữ liệu(PDF) 83 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Advanced power management system IC with embedded LIN and high speed CAN transceiver supporting CAN Partial Networking
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L99PM72PXP
ST SPI
Doc ID 023553 Rev 3
83/128
6.1.10
Read and Clear Status Operation
The ‘Read and Clear Status’ operation starts with a Command Byte followed 2 data bytes.
The number of data bytes is specified in the <SPI-frame-ID>. The content of the data bytes
is ‘don’t care’. The content of the addressed Status Register is transferred to SDO within the
same frame (‘in-frame response’) and is subsequently cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all Status registers (incl. the
<Global Status> register). The Configuration Register is read by this operation.
OC0, OC1: operating code (10 for ‘read and clear status’ mode)
A0 to A5: address bits
Format of data shifted out at SDO during ‘Read and Clear Status’ operation
Table 61.
Read and clear status command format: command byte
MSB
LSB
Op Code
Address
1
0
A5
A4
A3
A2
A1
A0
Table 62.
Read and clear status command format: data byte 1
MSB
LSB
0
0
00
00
0
0
Table 63.
Read and clear status command format: data byte 2
MSB
LSB
0
0
00
00
0
0
Table 64.
Format of data shifted out at SDO during read and clear status: global
status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Communication
error
Not (chip reset OR
comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Table 65.
Format of data shifted out at SDO during read and clear status:
data byte 1
MSB
Previous content of addressed register
LSB
D15
D14
D13
D12
D11
D10
D9
D8



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