L99PM72PXP datasheet(71/128 Pages) STMICROELECTRONICS

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L99PM72PXP

Electrical specifications

Doc ID 023553 Rev 3

71/128

thold DI

DI hold time

V1 = 5 V

200

—

tr in

rise time of input signal DI, CLK,

CSN

V1 =5 V

—

100

tf in

fall time of input signal DI, CLK,

CSN

V1 =5 V

—

100

See Figure 35: SPI input timing.

Table 39.

Output: DO

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDOL

output low level

V1 =5V; ID =-4mA

0.5

VDOH

output high level

V = 5 V; ID =4mA

4.5

IDOLK

tristate leakage current

VCSN =V1; 0 V < VDO <V1

-10

µA

CDO

tristate input capacitance

VCSN =V1;

0V < V1 <5.3 V

(1)

Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 40.

DO timing(1)

See Figure 36: SPI output timing (part 1).

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tr DO

DO rise time

CL =100 pF; ILOAD = -1 mA

—

100

tf DO

DO fall time

CL =100 pF; ILOAD =1mA

—

100

ten DO tri L

DO enable time from

tristate to low level

CL =100 pF; ILOAD =1mA;

pull-up load to V1

—50

250

tdis DO L tri

DO disable time from

low level to tristate

CL =100 pF; ILOAD =4mA;

pull-up load to V1

—50

250

ten DO tri H

DO enable time from

tristate to high level

CL =100 pF; ILOAD =-1mA;

pull-down load to GND

—50

250

tdis DO H tri

DO disable time from

high level to tristate

CL =100 pF; ILOAD =-4mA;

pull-down load to GND

—50

250

td DO

DO delay time

VDO <0.3 V1; VDO >0.7 V1;

CL =100 pF

—50

250

Table 41.

CSN timing(1)

See Figure 37: SPI CSN - output timing.

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tCSN_HI,min

Minimum CSN HI

time, active mode

Transfer of SPI-command to

Input Register

6µs

tCSNfail

CSN low timeout

Table 38.

DI timing(1) (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

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