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L99PM72PXP bảng dữ liệu(PDF) 122 Page - STMicroelectronics |
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L99PM72PXP bảng dữ liệu(HTML) 122 Page - STMicroelectronics |
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122 / 128 page ![]() ST SPI L99PM72PXP 122/128 Doc ID 023553 Rev 3 6.2.26 Status Register 4 Table 142. Status register 4: command and data bytes Command byte 1st data byte 2nd data byte Read/write Address Bit <15:8> Bit <7:0> x x 0 1 0 1 0 0 Data, 8bit Data, 8 bit Table 143. Control register 4, data bytes 1st data byte <15:8> 2nd data byte <7:0> Function Group Diagnosis 5 Diagnosis 6 Table 144. Status register 4, bits Bit Name Comment Information storage 15 SWRD_15 Status flag for Read operation to Selective Wakeup relevant Registers 0: Read not done 1: Read done See also Section 2.10: Serial Peripheral Interface (ST SPI Standard 3.0) Automatically cleared by a write 14 SWRD_14 13 SWRD_13 12 SWRD_12 11 SWRD_11 10 SWRD_10 9 SWRD_9 8 SWRD_8 7 SWRD_7 6 SYS_ERR This bit is a logical OR combination of NOT(SWRD_x) OR OSC_Fail OR FD_ERR The selective wake feature cannot be enabled (SW_EN = 1) if SYS_ERR = 1 In case of a SYS_ERR the selective wake-up feature is disabled (SW_EN = 0) Live bit be updated while the change of SWRD_x, OSC_Fail and FD_ERR. If SWRD_x are all 1, OSC_Fail is 0 and FD_ERR is 0, this bit is 0, otherwise this bit is 1. 5 TX_SYNC Status flag for Synchronous Reference oscillator of the Transceiver. Indicates that the last received frame was decoded correctly 0: Not synchron 1: Synchron Live bit updated after each sent CAN frame |
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