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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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L99PM72PXP bảng dữ liệu(PDF) 121 Page - STMicroelectronics |
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L99PM72PXP bảng dữ liệu(HTML) 121 Page - STMicroelectronics |
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121 / 128 page  L99PM72PXP ST SPI Doc ID 023553 Rev 3 121/128 13 Device_state State from which the device woke up Bit is latched until a “read and clear access” after a “read and clear access”, the device state is updated. After a wake up, device state is: 01: V1_standby or 10: VBat_standby 12 Device state_2 Device state_1 State from which the device woke up 00 Active 01 V1_standby 10 VBat_standby 11 Flash 11 V1_fail V1 fail (V1 < 2 V for t > 2 µs) event occurred since last read out Bit is latched until a “read and clear access” 10 V1_restart_2 Number of TSD2 events which caused a restart of V1 regulator (7 TSD2 events forces the device into VBat_standby) Bits are not clearable; is cleared automatically if no additional TSD2 event occurs within 1min. 9 V1_restart_1 8 V1_restart_0 7 WD_fail_3 Number of missing watchdog triggers (15 missing watchdog trigger forces the device into VBat_standby) Bits are not clearable; is cleared with a proper Watchdog trigger 6 WD_fail_2 5 WD_fail_1 4 WD_fail_0 3 Forced_sleep_WD Device was forced to VBat_standby mode because of multiple watchdog errors Bits are latched until a read and clear access 2 Forced_sleep_ TSD2_SHTV1 Device was forced to VBat_standby or multiple thermal shutdown events or a short on V1 during startup. 1 WD_timer_state_1 Status of watchdog counter of selected watchdog timing Bits are not clearable 0 WD_timer_state_0 WD_timer_state _1 WD_timer_state _0 Counter 0 0 0 – 33% 0 1 33 – 66% 1 1 66 – 100% Table 141. Status register 3, bits (continued) Bit Name Comment Information storage |
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