L9805E datasheet(84/125 Pages) STMICROELECTRONICS

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On-chip peripherals

L9805E

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Bit 2 = FSYN Fast Synchronization



Read/Set/Clear

Set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for

only 11 recessive bits in a row.

Cleared by software to enable the standard resynchronization when leaving standby mode,

i.e. wait for 128 sequences of 11 recessive bits.

Bit 1 = WKPS Wake-up Pulse

Read/Set/Clear

Set by software to generate a dominant pulse when leaving standby mode.

Cleared by software for no dominant wake-up pulse.

Bit 0 = RUN CAN Enable

Read/Set/Clear

Set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11

recessive bits if FSYN is set.

Cleared by software to request a switch to the standby or low-power mode as soon as any

on-going transfer is complete. Read-back as 1 in the meantime to enable proper signalling

of the standby state. The CPU clock may therefore be safely switched OFF whenever RUN

is read as 0.

BAUD RATE PRESCALER REGISTER (BRPR)

Adress: 005Dh - Read/Write in Standby mode

Reset Value: 00h

RJW[1:0] determine the maximum number of time quanta by which a bit period may be

shortened or lengthened to achieve resynchronization.

tRJW = tCAN * (RJW + 1)

BRP[5:0] determine the CAN system clock cycle time or time quanta which is used to build

up the individual bit timing.

tCAN = tCPU * (BRP + 1)

Where tCPU = time period of the CPU clock.

The resulting baud rate can be computed by the formula:

Note:

Writing to this register is allowed only in Standby mode to prevent any accidental CAN

protocol violation through programming errors.

BIT TIMING REGISTER (BTR)

Adress: 005Eh - Read/Write in Standby mode

Reset Value: 23h

RJW1

RJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

CPU

BRP





BS1

BS2





--------------------------------------------------------------------------------------------------

BS22

BS21

BS20

BS13

BS12

BS11

BS10

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