L9805E datasheet(80/125 Pages) STMICROELECTRONICS

80 / 125 page

On-chip peripherals

L9805E

80/125

Figure 43.

CAN error state diagram

Bit timing logic

The bit timing logic monitors the serial bus-line and performs sampling and adjustment of

the sample point by synchronizing on the start-bit edge and resynchronizing on following

edges.

Its operation may be explained simply when the nominal bit time is divided into three

segments as follows:

●

Synchronisation segment (SYNC_SEG): a bit change is expected to lie within this

time segment. It has a fixed length of one time quanta (1 x tCAN).

●

Bit segment 1 (BS1): defines the location of the sample point. It includes the

PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable

between 1 and 16 time quanta but may be automatically lengthened to compensate for

positive phase drifts due to differences in the frequency of the various nodes of the

network.

●

Bit segment 2 (BS2): defines the location of the transmit point. It represents the

PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8

time quanta but may also be automatically shortened to compensate for negative

phase drifts.

●

Resynchronization Jump Width (RJW): defines an upper bound to the amount of

lengthening or shortening of the bit segments. It is programmable between 1 and 4 time

quanta.

To guarantee the correct behaviour of the CAN controller, SYNC_SEG + BS1 + BS2 must

be greater than or equal to 5 time quanta.

For a detailed description of the CAN resynchronization mechanism and other bit timing

configuration constraints, please refer to the CAN Specification - Bosch - Version 2.

As a safeguard against programming errors, the configuration of the Bit Timing Register

(BTR) is only possible while the device is in STANDBY mode.

ERROR PASSIVE

When TECR or RECR > 127, the EPSV bit gets set

When TECR and RECR < 128,

and the EPSV bit gets cleared

ERROR ACTIVE

BUS OFF

When TECR > 255 the BOFF bit gets set

When 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

the EPSV bit gets cleared

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