L9805E datasheet(76/125 Pages) STMICROELECTRONICS

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On-chip peripherals

L9805E

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Hardware blocks

The CAN controller contains the following functional blocks (refer to Figure 40):

●

ST7 Interface: buffering of the ST7 internal bus and address decoding of the CAN

registers.

●

TX/RX Buffers: three 10-byte buffers for transmission and reception of maximum length

messages.

●

ID Filters: two 12-bit compare and don’t care masks for message acceptance filtering.

●

PSR: page selection register (see memory map).

●

BRPR: clock divider for different data rates.

●

BTR: bit timing register.

●

ICR: interrupt control register.

●

ISR: interrupt status register.

●

CSR: general purpose control/status register.

●

TECR: transmit error counter register.

●

RECR: receive error counter register.

●

BTL: bit timing logic providing programmable bit sampling and bit clock generation for

synchronization of the controller.

●

BCDL: bit coding logic generating a NRZ-coded datastream with stuff bits.

●

SHREG: 8-bit shift register for serialization of data to be transmitted and parallelisation

of received data.

●

CRC: 15-bit CRC calculator and checker.

●

EML: error detection and management logic.

●

CAN Core: CAN 2.0B passive protocol controller.

Modes of operation

The CAN Core unit assumes one of the seven states described below:

●

STANDBY. Standby mode is entered either on a chip reset or on resetting the RUN bit

in the Control/Status Register (CSR). Any on-going transmission or reception operation

is not interrupted and completes normally before the Bit Time Logic and the clock

prescaler are turned off for minimum power consumption. This state is signalled by the

RUN bit being read-back as 0.

Once in standby, the only event monitored is the reception of a dominant bit which

causes a wake-up interrupt if the SCIE bit of the Interrupt Control Register (ICR) is set.

The STANDBY mode is left by setting the RUN bit. If the WKPS bit is set in the CSR

directly.

It is important to note that the wake-up mechanism is software-driven and therefore

carries a significant time overhead. All messages received after the wake-up bit and

before the controller is set to run and has completed synchronization are ignored.

●

WAKE-UP. The CAN bus line is forced to dominant for one bit time signalling the wake-

up condition to all other bus members.

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