STW4810CHDRLF datasheet(36/78 Pages) STMICROELECTRONICS

36 / 78 page

Functional description

STw4810

36/78

Fast switching from low current to normal mode.

The regulator is in ‘low current mode’ when multimedia processor is in sleep

mode. PWREN signal indicates that the multimedia processor is about to switch to

run mode. VDDOK signal indicates to the multimedia processor that all supplies

are in the specified range.

Note:

The definition of sleep mode is given in 4.2.3: Sleep mode section.

●

Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●

Default setting defined by start-up configuration.

4.3.4

VPLL

This LDO is dedicated to the multimedia processor PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V) power

supply with 10 mA max full load (Power Control Registers -

Table 27 and Table 28).

Main features

●

Programmable output voltage, (VPLL_SEL[1:0] bits of power control register -

Table 27

and

Table 28)

●

Two power domains:

–

‘Normal mode’ 10 mA full load

–

‘Power down mode’ or ‘standby mode’ when regulators are switched off and there

is no power consumption (EN_VPLL bit of power control register -

Table 28)

●

Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●

Default setting defined by start-up configuration.

4.3.5

VANA

This LDO is dedicated to the multimedia processor analogue function (2.5 V) power supply

with 10 mA full load.

Main features:

●

2.5 V output voltage,

●

Two power domains

–

‘Normal mode’ 10 mA full load

–

‘Power down mode’ or ‘standby mode’ when regulators are switched off and there

is no power consumption (EN_VANA bit of power control register -

Table 29),

●

Default setting defined by start-up configuration.

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