STW4810CHDRLF datasheet(34/78 Pages) STMICROELECTRONICS

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Functional description

STw4810

34/78

4.3

Power management module

STw4810 includes several regulators that supply the multimedia processor and its

peripherals. All regulators can work in different modes depending on the processor needs.

When the STw4810 is in ‘low current mode’”, the output current is reduced to save energy

via the lower quiescent current. The nominal mode is called high power mode (HPM). The

mode is selected by PWREN signal according to both multimedia processor and STw4810

state.

When PWREN = “0”, sleep mode is selected. HPM is selected as default when PWREN =

“1”.

Each regulator has a dedicated battery power supply. It can be powered down by a signal

called PDN_regulator_name as shown in the

Figure 2: STw4810 block diagram. In this

mode, the regulator is switched off and only a leakage current is present (max. 1µA).

VCORE, VAUX and VPLL output voltages are programmable, through main I2C interface,

using the “Regulator”_SEL[x:0] bits of the power control registers (

Table 22 to Table 27).

In addition, an output current limitation prevents high current delivery in case of output short

circuit.

All multimedia processor power supplies have the same soft start to prevent leakage in the

multimedia processor device during the start-up phase. There is an exception with VAUX

which can be started independently.

4.3.1

Bandgap, biasing and references

Figure 10.

Block diagram of biasing and references of the device

All internal

references

VREF_18

All internal

biasing

Bias generator

Voltage reference

control

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