STW4810CHDRLF datasheet(14/78 Pages) STMICROELECTRONICS

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Functional description

STw4810

14/78

Functional description

4.1

Introduction

The STw4810 integrates all the power supplies for a multimedia processor as well as

memories and peripherals:

●

Two switched mode power supply regulators: one for the multimedia processor core,

one for multimedia processor I/Os and memories

●

Three low-drop output regulators for multimedia processor analog supplies (PLL and

others) and auxiliary components

●

USB OTG FS/LS physical interface

●

MMC card power supplies and level shifters

●

Multimedia processor supply monitoring / power-on reset and power supply alarms /

interrupt management

●

Two serial I2C communication interfaces; one to control the devices (SDA, SCL) and

one to control the USB (USBSDA, USBSCL).

4.2

Digital control module

This module describes the interfaces used to program the device and the related registers.

4.2.1

State machine

Description of each states: (

Figure 3.)

Off: In this mode the STw4810 is switched off. Off is when PON=0, when battery level is

under 2.4 V or when thermal shutdown is activated. There is no multimedia processor power

supply. The only active cell is the USB cable detection and VBAT level detection.

OSC_START: Oscillator is enabled and the power up module is waiting for the rising edge of

the internal signal OSC_OK to start power up sequence. This state duration is 300 µs.

START_BIAS: Bias, reference and thermal shut-down are enabled, a counter is activated to

wait for rising edge of internal signals PDN_regulators. This state duration has a typical

value of 7.77 ms and a worst case value of 9.46 ms.

START_PM: after a 1 ms wait, multimedia processor power supplies are available

(VIO_VMEM, VCORE, VPLL, and VANA). The device can allow I2C communication, output

power supply monitoring and application (USB,SD/MMC).

OFF2: STw4810 is waiting for the 32 kHz multimedia processor signal. This state has an

indeterminate duration. If 32kHz is present during the states describes above, it has no

effect. The 32 kHz signal is taken into account by STw4810 only when the ‘VDDOK’ ball is

high, that is at the end of START_PM state.

Reset: STw4810 forces a reset during 10*32 kHz period before setting PORn high.

INT_OSC: The STw4810 can work without MASTER_CLK via its internal oscillator. The

device waits for an external clock detection before switching to the external clock. When

receiving a rising edge on PWREN ball (coming from multimedia processor) or on

TCXO_EN ball (coming from modem), STw4810 answers by asserting to “1” the

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