DP83849IFVSSLASHNOPB.A datasheet(47/108 Pages) TI2

tên linh kiện	DP83849IFVS/NOPB.A

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DP83849IF

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SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

The

DP83849IF

requires

single

initialization

sequence

bits

preamble

following

hardware/software reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in

conjunction with a continuous MDC, or the management access made to determine whether Preamble

Suppression is supported.

While the DP83849IF requires an initial preamble sequence of 32 bits for management initialization, it

does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit

between management transactions is required as specified in the IEEE 802.3u specification.

6.6.4

Simultaneous Register Write

The DP83849IF incorporates a mode which allows simultaneous write access to both Port A and B

(RBR, address 17h) in Port A.

As long as this bit remains set, subsequent writes to Port A will write to registers in both ports.

MAC Interface

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DP83849IFVS/NOPB.A bảng dữ liệu(PDF) 47 Page - Texas Instruments