FN8808 datasheet(26/44 Pages) RENESAS

26 / 44 page

ISL78227

FN8808 Rev.6.02

Page 26 of 43

Feb 28, 2025

2.5V PWM signal at phase node of Q1 and Q2 has around 25mV at

VREF_TRK, which is 1.56% of 1.6V reference. This will not affect the

boost output voltage because of the limited bandwidth of the

system. A frequency of 400kHz is recommended for the PWM signal

at the TRACK pin. Lower frequency at the TRACK input is possible,

but VREF_TRK has a higher AC ripple. Bench test evaluation is

needed to make sure the output voltage is not affected by this

VREF_TRK AC ripple.

When ATRK/DTRK = VCC (ATRK mode), the MUX connects the

TRACK pin voltage to the input of the 2-stage RC filter

R1/C1/R2/C2. The TRACK pin accepts analog signal inputs, with the

Gm1’s VREF_TRK input equal to the voltage on the TRACK pin. The

low-pass filter has the same cutoff frequency of 1.75kHz.

If not used, the TRACK pin should be left floating or tied to VCC

and the internal VREF_1.6V working as the reference.

The TRACK function is enabled before the SS pin soft-start. The

VOUT reference can be controlled by TRACK inputs at start-up.

After the SS pin ramps up to the upper clamp AND the VREF_TRK

reaches 0.3V, the upper side FET is controlled to turn on

gradually to achieve smooth transitions from DCM mode to CCM

mode, of which the transition duration is 100ms (when set at

CCM mode). After this transition, PGOOD is allowed to be pulled

HIGH as long as output voltage is in regulation (within OV/UV

threshold).

The maximum TRACK reference frequency for the boost VOUT to

track (VREF_TRK at Figure 51) is limited by the boost converter's

loop bandwidth. Generally, the tracking reference signal’s

frequency should be 10 times lower than the boost loop

crossover frequency. Otherwise, the boost output voltage cannot

track the tracking reference signal and the output voltage is

distorted. For example, for a boost converter with 4kHz loop

crossover frequency, the boost can track reference signals up to

400Hz, typically. Figures 23 and 24 on page 19 show

performances tracking 100Hz and 300Hz signals.

PEAK CURRENT MODE CONTROL

As shown in Figure 3 on page 7, each phase’s PWM operation is

initialized by the fixed clock for this phase from the oscillator

(refer to “Oscillator and Synchronization” on page 27). The clocks

for Phase 1 and Phase 2 are 180° out of phase. The low-side

MOSFET is turned on (LGx) by the clock (after a dead time delay

of tDT1) at the beginning of a PWM cycle and the inductor current

ramps up. The ISL78227’s Current Sense Amplifiers (CSA) sense

each phase inductor current and generate the current sense

signal ISENx. The ISENx is added with the compensating slope and

generates VRAMPx. When VRAMPx reaches the error amplifier

(Gm1) output voltage, the PWM comparator is triggered and LGx

is turned off to shut down the low-side MOSFET. The low-side

MOSFET stays off until the next clock signal comes for the next

cycle.

After the low-side MOSFET is turned off, the high-side MOSFET

turns on after dead time tDT2. The turn-off time of the high-side

MOSFET is determined by either the PWM turn-on time at the

next PWM cycle, or when the inductor current becomes zero if

the Diode Emulation mode is selected.

Multiphase Power Conversion

For an n-phase, interleaved, multiphase boost converter, the

PWM switching of each phase is distributed evenly with 360°/n

phase shift. The total combined current ripples at the input and

output are reduced where smaller input and output capacitors

can be used. In addition, it is beneficial to have a smaller

equivalent inductor for a faster loop design. Also in some

applications, especially in a high current case, multiphase makes

it possible to use a smaller inductor for each phase rather than

one big inductor (single-phase), which is sometimes more costly

or unavailable on the market at the high current rating. Smaller

size inductors also help to achieve low profile design.

The ISL78227 is a controller for 2-phase interleaved converter

where the two phases are operating with 180° phase shift,

meaning each PWM pulse is triggered 1/2 of a cycle after the

start of the PWM pulse of the previous phase. Figure 52 on

page 27 illustrates the interleaving effect on input ripple current.

The AC component of the two phase currents (IL1 and IL2) are

interleaving each other and the combined AC current ripple

(IL1 + IL2) at input are reduced. Equivalently, the frequency of the

AC inductor ripple at input is two times of the switching

frequency per phase.

FIGURE 51. TRACK FUNCTION BLOCK DIAGRAM

TRACK

VREF_2.5V

20p

2.5*D

Gm1

VREF_1.6V

VREF_TRK

COMP

ATRK/DTRK

ATRAK/

DTRK

IC INTERNAL CIRCUITS

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