ISL78227

FN8808 Rev.6.02

Page 5 of 43

Feb 28, 2025

BOOT2

16

Provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external

N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor is recommended between the BOOT2 and PH2 pins.

In the typical configuration, PVCC provides the bias to BOOT2 through a fast switching diode.

In applications in which a high-side driver is not needed (for example, standard boost applications), BOOT2 is recommended

to be connected to ground. The ISL78227 IC can detect BOOT2 being grounded during start-up and both the Phase 1 and

Phase 2 high-side drivers are disabled. In addition, PH1 and PH2 should also be tied to ground.

UG2

17

Phase 2 high-side gate driver output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2 to

ground.

PH2

18

Represents the return path for the Phase 2 high-side gate drive. Connect this pin to the source of the Phase 2 high-side

MOSFETs and the drain of the low-side MOSFETs.

LG2

19

Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates.

PGND

20

Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current, so traces connecting from

this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short as possible. All

sensitive analog signal traces should not share common traces with this driver return path. Connect this pin to the ground

copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through several vias as close as

possible to the IC.

PVCC

21

Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx through

diodes), and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps to filter out

the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic capacitor should

be used between PVCC and PGND. Refer to “Internal 5.2V LDO” on page 36 for more details.

LG1

22

Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates.

PH1

23

Represents the return path for the Phase 1 high-side gate drive. Connect this pin to the source of the Phase 1 high-side

MOSFETs and the drain of the low-side MOSFETs.

UG1

24

Phase 1 high-side MOSFET gate drive output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2

to ground.

BOOT1

25

Provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external

N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between BOOT1 and PH1 pins. In

a typical configuration, PVCC provides the bias to BOOT1 through a fast switching diode.

In applications in which a high-side driver is not needed (for example, standard boost applications), BOOT1 is recommended

to be connected to ground. The ISL78227 IC can detect BOOT1 being grounded during start-up and both the Phase 1 and

Phase 2 high-side drivers are disabled. In addition, PH1 and PH2 should also be tied to ground.

VIN

26

Connect the supply rail to this pin. Typically, connect the boost input voltage to this pin. The VIN pin can also be supplied by a

separate input source independent from the boost power stage input source. This pin is connected to the input of the internal linear

regulator, generating the power necessary to operate the chip. The DC voltage applied to VIN should not exceed 55V during normal

operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection stops it from switching to

protect itself. Refer to “Input Overvoltage Fault Protection” on page 34 for more details.

ISEN1N

27

The ISEN1N pin is the negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses the

Phase 1 inductor current through a power current sense resistor in series with the inductor. The sensed current signal is used

for current mode control, peak current limiting, average current limiting, and diode emulation.

ISEN1P

28

Positive potential input to the Phase 1 current sense amplifier.

ISEN2N

29

Negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses the Phase 2 inductor

current through a power current sense resistor in series with the inductor. The sensed current signal is used for current mode

control, peak current limiting, average current limiting, and diode emulation.

ISEN2P

30

Positive phase input to the Phase 2 current sense amplifier.

ATRK/DTRK

31

Logic input pin to select the input signal format options for the TRACK pin. Pull this pin HIGH for the TRACK pin to accept

analog input signals. Pull this pin LOW for the TRACK pin to accept digital input signals. Refer to “Digital/Analog Track

Function” on page 25 for more details.

RDT

32

A resistor connected from this pin to ground programs the dead times between UGx OFF to LGx ON and LGx OFF to UGx ON

to prevent shoot-through. Refer to “Driver Configuration” on page 24 for the selection of RDT.

SGND

-

Signal ground bottom pad to which to refer the internal sensitive analog circuits. Also serves as thermal pad. Connect this

pad to a large ground plane. Put as many vias as possible in this pad connecting to the ground copper plane to help reduce the

IC’s JA. In layout power flow planning, avoid noisy, high frequency pulse current flow through the SGND area.

Functional Pin Description(Continued)

PIN NAME

PIN #

DESCRIPTION