FN8808 datasheet(33/44 Pages) RENESAS

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ISL78227

FN8808 Rev.6.02

Page 33 of 43

Feb 28, 2025

AUTOMATIC PHASE DROPPING/ADDING

When the Phase Drop function is enabled, the ISL78227

automatically drops or adds Phase 2 by comparing the VIMON to

the phase dropping/adding thresholds. VIMON is proportional to

the average input current indicating the level of the load.

The phase dropping mode is not allowed with external

synchronization.

Phase Dropping

When load current drops and VIMON falls below 1.1V, Phase 2 is

disabled. For better transient response during phase dropping,

the ISL78227 gradually reduces the duty cycle of the phase from

steady state to zero, typically within 8 to 10 switching cycles. This

gradual dropping scheme helps smooth the change of the PWM

signal and stabilizes the system when phase dropping happens.

From Equations 13 and 14, the phase dropping current threshold

level for the total, 2-phase boost input current can be calculated

by Equation 16.

Phase Adding

Phase adding is decided by the two mechanisms listed below.

Phase 2 is added immediately if either of the two following

conditions are met.

1. VIMON >1.15V, the IMON pin voltage is higher than phase

adding threshold 1.15V. The phase adding current threshold

level for the total 2-phase boost input current can be

calculated by Equation 17.

2. ISENx >80µA (OC1), individual phase current triggers OC1.

The first is similar to the phase dropping scheme. When the load

increases causing VIMON >1.15V, Phase 2 is added back

immediately to support the increased load demand. Because the

IMON pin normally has large RC filter and VIMON is average

current signal, this mechanism has a slow response and is

intended for slow load transients.

The second mechanism is intended to handle the case when load

increases quickly. If the quick load increase triggers OC1

(ISENx >80µA) in either of the two phases, Phase 2 is added back

immediately.

After Phase 2 is added, the phase dropping function is disabled

for 1.5ms. After this 1.5ms expires, the phase dropping circuit is

activated again and Phase 2 can be dropped automatically as

usual.

DIODE EMULATION AT LIGHT-LOAD CONDITION

When the Diode Emulation mode (DE) is selected to be enabled

(Mode 1 and Mode 2 in Table 2), the ISL78227 has cycle-by-cycle

diode emulation operation at light load achieving Discontinuous

Conduction Mode (DCM) operation. With DE mode operation,

negative current is prevented and the conduction loss is reduced,

therefore, high efficiency can be achieved at light-load

conditions.

Diode emulation occurs during t5-t8 (on Figure 58 on page 29),

regardless of the DE/PHDRP operating modes (Table 2).

PULSE SKIPPING AT DEEP LIGHT-LOAD CONDITION

If the converter enters Diode Emulation mode and the load is still

reducing, eventually pulse skipping occurs to increase the deep

light-load efficiency. Either Phase 1, Phase 2, or both, pulse skips

at these deep light-load conditions.

Fault Protections/Indications and Current

Limiting

The ISL78227 is implemented with comprehensive fault

protections/indications and current limitings to design a highly

reliable boost converter. Most of the fault protections’ responses

can be selected to be either Hiccup or Latch-off by configuring

the HIC/LATCH pin, which offers the flexibility upon the specific

requirements for different applications.

SELECTABLE HICCUP OR LATCH-OFF FAULT RESPONSE

Table 3 on page 34 lists the fault protections that can have either

Hiccup or Latch-off fault response determined by HIC/LATCH pin

configurations.

• When the HIC/LATCH pin is pulled high (VCC), the fault response

is in Hiccup mode.

• When the HIC/LATCH pin is pulled low (GND), the fault response is

in Latch-off mode.

In Hiccup mode, the device stops switching when a fault

condition in Table 3 on page 34 is detected, and restarts from

soft-start after 500ms (typical). This operation is repeated until

fault conditions are completely removed.

In Latch-off mode, the device stops switching when a fault

condition in Table 3 on page 34 is detected and PWM switching

being kept off even after fault conditions are removed. In

Latch-off status, the internal LDO is alive to keep PVCC voltage

regulated. By either toggling the EN pin or cycling VCC/PVCC

below the POR threshold restarts the system.

TABLE 2. CCM/DE/PH_DROP MODE SETTING (DE/PHDRP PIN)

MODE NUMBER

(NAME)

DE/PHDRP PIN

SETTING

DE MODE

PHASE-DROP

MODE

1 (DE)

VCC

Enabled

Disabled

2 (DE+PH_DROP)

FLOAT

Enabled

3 (CCM)

GND

Disabled

(EQ. 16)

IINphDRP

1.1

RIMON

------------------- 17 10



–







 RSET

RSEN

---------------- 8



 

(EQ. 17)

IINphADD

1.15

RIMON

------------------- 17 10



–







 RSET

RSEN

---------------- 8



 

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