FN8808 datasheet(29/44 Pages) RENESAS

29 / 44 page

ISL78227

FN8808 Rev.6.02

Page 29 of 43

Feb 28, 2025

Refer to Figure 57 for the selection of RBLANK resistor and

tMINON time. A 5kΩ resistor is recommended as the minimum

RBLANK resistor.

Operation Initialization and Soft-Start

Before converter initialization, the EN pin voltage must be higher

than its rising threshold and the PVCC/VCC pin must be higher

than the rising POR threshold. When these conditions are met, the

controller begins initialization and soft-start. Figure 58 shows the

ISL78227 internal start-up timing diagram from the power-up to

soft-start.

Assuming input voltage is applied to the VIN pin before t1 and VCC

is connected to PVCC, as shown on Figure 58, the descriptions for

start-up procedures are described as follows:

t1 - t2: The enable comparator holds the ISL78227 in shutdown

until the VEN rises above 1.2V (typical) at the time of t1. During

t1 - t2, VPVCC/VCC gradually increases and reaches the internal

Power-On Reset (POR) rising threshold 4.5V (typical) at t2.

t2 - t3: During t2 - t3, the ISL78227 self-calibrates to detect

certain pin configurations (HIC/LATCH, DE/PHDRP,

ATRK/DTRAK) to latch in the selected operation modes. The time

duration for t2 - t3 is typically 195µs.

t3 - t4: During this period, the ISL78227 waits until the internal

PLL circuits are locked to the preset oscillator frequency. When

PLL locking is achieved at t4, the oscillator generates output at

the CLK_OUT pin. The time duration for t3 - t4 depends on the

PLLCOMP pin configuration. The PLL is compensated with a

series resistor-capacitor (RPLL and CPLL1) from the PLLCOMP pin

to GND and a capacitor (CPLL2) from PLLCOMP to GND. At the

300kHz switching frequency, typical values are RPLL = 3.24kΩ,

CPLL1 = 6.8nF, and CPLL2 = 1nF. With this PLLCOMP

compensation, the time duration for t3 - t4 is around 0.7ms.

t4 - t5: During this period, the PLL locks the frequency t4 and the

system prepares to soft-start. The ISL78227 has one unique

feature to pre-bias the SS pin voltage to be equal to VFB during

t4 - t5, which is around 50µs.

t5 - t6: At t5, the soft-start ramps up at the SS pin (VSSPIN) and

the COMP voltage starts to ramp up as well. Drivers are enabled

but not switching during t5 - t6 because the COMP is still below

the current sense ramp offset. The device operates in diode

emulation mode during soft-start period t5 - t8. The slew rate of

the SS ramp and the duration of t5 - t8 are determined by the

capacitor used at the SS pin.

t6 - t7: At t6, COMP is above the current sense ramp offset and

the drivers start switching. Output voltage ramps up while FB

voltage is following SS ramp during this soft-start period. At t7,

output voltage reaches the regulation level and FB voltage

reaches VREF_1.6V.

t7 - t8: At this stage, SS continues ramping up until it reaches the

SS clamp voltage (VSSPCLAMP) 3.47V at t8, indicating the SS pin

ramp-up is completed. At t8, the ISL78227 generates an internal

SS_DONE signal, which goes HIGH when both VSSPIN =

VSSPCLAMP (3.47V) and VREF_TRK ≥ 0.3V (as shown in Figure 3

on page 7). This indicates the soft-start has completed.

t8 - t9: After t8, a delay time of either 0.5ms or 100ms is inserted

before the PGOOD pin is released HIGH at t9, depending on the

selected mode (refer to Table 2 on page 33).

1. If the DE/PHDRP pin = VCC or FLOAT to have DE mode

selected, the PGOOD rising delay from VSSPIN = VSSPCLAMP

(3.47V) and VREF_TRK ≥0.3V to PGOOD rising is 0.5ms.

2. If the DE/PHDRP pin = GND to have CCM mode selected, the

PGOOD rising delay from VSSPIN = VSSPCLAMP (3.47V) and

VREF_TRK ≥0.3V to PGOOD rising is 100ms, during which

period the device is transitioning from DE mode to CCM mode.

The high-side gate UGx is controlled to gradually increase the

ON-time to finally merge with CCM ON-time. This synchronous

MOSFET “soft-ON” feature is unique and ensures smooth

transition from DCM mode to CCM mode after soft-start

completes. More importantly, this “SYNC FET soft-ON”

function eliminates the large negative current, which often

FIGURE 57. tMINON vs RBLANK

100

150

200

250

300

350

400

450

500

1520253035

4045

505560

6570

RBLANK (k)

FIGURE 58. CIRCUIT INITIALIZATION AND SOFT-START

1.2V

POR_R

PVCC/VCC

PLLCOMP

CLKOUT

COMP

COMP_Ramp_Offset

VFB

t1 t2 t3

t4t5 t6

t8 t9

PGOOD

FN8808 bảng dữ liệu(PDF) 29 Page - Renesas Technology Corp

FN8808 bảng dữ liệu(HTML) 29 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

bảng dữ liệu tải về

Link URL