FN8808 datasheet(25/44 Pages) RENESAS

25 / 44 page

ISL78227

FN8808 Rev.6.02

Page 25 of 43

Feb 28, 2025

PWM Control

The ISL78227 uses fixed frequency peak current mode control

architecture. As shown in Figure 3 on page 7 and the typical

schematic diagram (Figure 4 on page 8), error amplifier (Gm1)

compares the FB pin voltage and reference voltage and

generates a voltage loop error signal at the COMP pin. This error

signal is compared with the current ramp signal (VRAMP) by the

PWM comparator. The PWM comparator output combined with

fixed frequency clock signal controls the SR flip-flop to generate

the PWM signals (refer to “Peak Current Mode Control” on

page 26).

OUTPUT VOLTAGE REGULATION LOOP

The resistor divider RFB2 and RFB1 from VOUT to FB (Figure 4 on

page 8) can be selected to set the desired VOUT. VOUT can be

calculated by Equation 2.

where in normal operation after soft-start, VREF can be either

VREF_1.6V or VREF_TRK, whichever is lower.

Gm1 has three inputs for reference voltage: soft-start ramp SS,

VREF_TRK, and VREF_1.6V. The Gm1 uses the lowest value

among SS, VREF_TRK, and VREF_1.6V. SS, VREF_TRK, and

VREF_1.6V are valid for Gm1 during and after soft-start. In

general operation, VREF_TRK is normally HIGH before soft-start

and SS normally ramps up from a voltage lower than VREF_TRK

and VREF_1.6V, in which case SS controls the output voltage

ramp-up during soft-start. After soft-start is complete, the user

can adjust VREF_TRK for the desired voltage. Because VREF_TRK

is valid before soft-start, setting VREF_TRK lower than SS can

make the SS ramp ineffective because Gm1 uses the lower

VREF_TRK voltage. In such a case, the VREF_TRK becomes the

real soft-start ramp that controls the output voltage ramp-up.

Digital/Analog Track Function

The TRACK input provides an external reference voltage to be

applied for the output voltage loop to follow, which is useful if the

user wants to change the output voltage as required. An example

is to employ envelope tracking technology in audio power

amplifier applications. The ISL78227 boost stage output is

powering the audio power amplifier stage input, where the boost

output tracks the music envelope signal applied at the TRACK

pin. Ultimately, higher system efficiency can be achieved.

The TRACK pin can accept either a digital signal or an analog

signal by configuring the ATRK/DTRK pin to be connected to

ground or VCC. Figure 51 on page 26 shows the track function

block diagram. VREF_TRK is fed into Gm1 as one of the

reference voltages. The Gm1 takes the lowest voltage of SS,

VREF_TRK, and VREF_1.6V as the actual reference. When

VREF_TRK is the lowest voltage, it becomes the actual reference

voltage for Gm1 and the output voltage can be adjusted with

TRACK signal changes. Regarding the effective VREF_TRK range:

• There is no limit for the minimum voltage on the TRACK pin,

but note the lower reference voltage and the lower voltage

feedback regulation accuracy. Note the SS_DONE signal is

checking VREF_TRK ≥0.3V as one of the conditions (refer to

Figure 58 on page 29 and the t8-t9 description on page 29).

Also, for the boost converter, the regulated output minimum

voltage is usually the input voltage minus the upper MOSFET’s

body diode drop, in which case, the corresponding voltage at

FB voltage is the minimum effective voltage for the VREF_TRK.

• The Gm1 takes the lowest voltage of SS, VREF_TRK, and

VREF_1.6V as the actual reference. The maximum effective

range for VREF_TRK is determined by VREF_1.6V or SS signal,

whichever is lower. For example, after soft-start, when the SS

pin equals to 3.47V (typical), the maximum effective voltage

for VREF_TRK is 1.6V (VREF_1.6V).

When ATRK/DTRK = GND (DTRK mode), the TRACK pin accepts

digital signal inputs. VREF_TRK (as one of the references input

for the error amplifier Gm1) equals to the average duty cycle

value of the PWM signal’s at the TRACK pin. As shown in

Figure 51 on page 26, the MUX is controlled by the ATRK/DTRK

pin configurations. When ATRK/DTRK = GND, the MUX connects

the output of the Q1 and Q2 switch bridge to the input of a

2-stage RC filter (R1, C1, R2, and C2). The PWM signal at the

TRACK pin controls Q1 and Q2 to chop the 2.5V internal

reference voltage. The phase node of Q1 and Q2 is a PWM signal

with accurate 2.5V amplitude and duty cycle D, where D is the

input PWM duty cycle on the TRACK input pin. The RC filter

smooths out the PWM AC components and the voltage

VREF_TRK after the RC filter becomes a DC voltage equal to

2.5V*D:

According to Equation 3, the PWM signals’ amplitude at the TRACK

pin does not affect the VREF_TRK accuracy and only the duty cycle

value changes the VREF_TRK value. In general, the VREF_TRK

reference accuracy is as good as the 2.5V reference. The built-in low

pass filter (R1, C1, R2, and C2) converts the PWM signal’s duty

cycle value to a low noise reference. The low pass filter has a

cutoff frequency of 1.75kHz and a gain of -40dB at 400kHz. The

FIGURE 50. DEAD TIME vs RDT, tDT1 REFERS TO UG FALLING TO LG

RISING, tDT2 REFERS TO LG FALLING TO UG RISING

100

150

200

250

300

10152025303540455055606570

RD T (k

)

tDT2

tDT1

VOUT VREF 1

RFB2

RFB1

---------------















(EQ. 2)

VREFTRK 2.5 D



(EQ. 3)

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