FN8808 datasheet(35/44 Pages) RENESAS

35 / 44 page

ISL78227

FN8808 Rev.6.02

Page 35 of 43

Feb 28, 2025

When the output voltage rises back above the VOUT_UV

threshold of 80% * VREF_1.6V plus 4% hysteresis, PGOOD is

released to be pulled high after a 0.5ms delay.

Equivalently, the VOUT undervoltage threshold is set at the same

percentage of VOUT target voltage VOUT_TARGET (set by

VREF_1.6V) because the device uses the same FB voltage to

regulate the output voltage with the same resistor divider

between VOUT and the FB pin (refer to Equation 2 on page 25).

Therefore, the VOUT undervoltage threshold is set at 80% of

VOUT_TARGET. According to Equation 2 on page 25, the VOUT

undervoltage protection threshold can be calculated using

Equation 19.

OVERCURRENT LIMITING AND FAULT PROTECTION

The ISL78227 has multiple levels of overcurrent

protection/limiting. Each phase’s peak inductor current is

protected from overcurrent conditions by limiting its peak

current. The combined total current is protected on an average

basis. Also, each phase is implemented with instantaneous,

cycle-by-cycle negative current limiting (OC_NEG_TH = -48µA).

Peak Current Cycle-by-Cycle Limiting (OC1)

Each individual phase’s inductor peak current is protected with

cycle-by-cycle peak current limiting (OC1) without triggering

Hiccup or Latch-off shutdown of the IC. The controller

continuously compares the CSA output current sense signal,

ISENx (calculated by Equation 11 on page 31) to an overcurrent

limiting threshold (OC1_TH = 80µA) in every cycle. When ISENx

reaches 80µA, the respective phase’s LGx is turned off to stop

inductor current further ramping up. In such a way, peak current

cycle-by-cycle limiting is achieved.

The equivalent cycle-by-cycle peak inductor current limiting for

OC1 can be calculated using Equation 20:

Negative Current Cycle-by-Cycle Limiting (OC_NEG)

Each individual phase’s inductor current is protected with

cycle-by-cycle negative current limiting (OC_NEG) without

triggering Hiccup or Latch-off shutdown of the IC. The controller

continuously compares the CSA output current sense signal,

ISENx, (calculated by Equation 11 on page 31) to a negative

current limiting threshold (OC_NEG_TH = -48µA) in every cycle.

When ISENx falls below -48µA, the respective phase’s UGx is

turned off to stop the inductor current further ramping down. In

such a way, negative current cycle-by-cycle limiting is achieved.

The equivalent negative inductor current-limiting level can be

calculated by Equation 21:

Peak Overcurrent Fault (OC2_PEAK) Protection

If either of the two individual phase’s current sense signals ISENx

(calculated by Equation 11 on page 31) reaches 105µA

(OC2_TH = 105µA) for three consecutive switching cycles, the

Peak Overcurrent fault (OC2_PEAK) is triggered. The ISL78227

responds with fault protection actions to shut down the PWM

switching and enters either Hiccup or Latch-off mode depending

on HIC/LATCH pin configuration as described in “Selectable

Hiccup or Latch-Off Fault Response” on page 33 and Table 3 on

page 34.

This fault protection is intended to protect the device by

shutdown (Hiccup or Latch-off) from the worst case condition

where OC1 cannot limit the inductor peak current.

This fault detection is active at the beginning of soft-start (t5 as

shown in the Figure 58 on page 29).

Under the selection of Hiccup response for the OC2_PEAK fault,

when both phases’ peak current sense signals ISENx no longer

trip the OC2_PEAK thresholds (105µA), the device returns to

normal switching and regulation through Hiccup soft-start.

The equivalent inductor peak current threshold for the

OC2_PEAK fault protection can be calculated by Equation 22:

Constant Current Control (CC)

A dedicated constant average Current Control (CC) loop is

implemented in the ISL78227 to control the input current to be

constant at overload conditions, which means constant input

power control under certain constant input voltage.

As shown in Figure 3 on page 7, the VIMON represents the total

input average current and is sent to the error amplifier Gm2 input to

be compared with the internal CC reference VREF_CC (1.6V). Gm2

output is driving the COMP voltage through a diode, DCC. Thus, the

COMP voltage can be controlled by either Gm1 output or Gm2

output through DCC depending on load conditions.

At normal operation without overloading, VIMON is lower than the

VREF_CC (1.6V at default). Therefore, Gm2 output is HIGH and DCC is

reversely blocked and not forward conducting. In this case, the

COMP voltage is controlled by the voltage loop error amplifier Gm1’s

output to have the output voltage regulated.

At input average current overloading case, when VIMON reaches

VREF_CC (1.6V), Gm2 output falls, DCC is forward conducting, and

Gm2 output overrides Gm1 output to drive COMP. In this way, the CC

loop overrides the voltage loop, meaning VIMON is controlled to be

constant and input average constant current operation is achieved.

Under certain constant input voltage, input CC makes input power

constant for the boost converter. Compared to peak current limiting

schemes, the average constant current control is more accurate to

control the average current to be constant, which is beneficial for the

user to accurately control the maximum average power for the

converter to handle.

The CC current threshold should be set lower than the OC1 peak

current threshold with margin. Generally, the OC1 peak current

threshold (per phase) is set 1.5 to 2 times higher than the CC

current threshold (here referred to per phase average current).

VOUTUV 0.8 1.6



RFB2

RFB1

---------------















(EQ. 19)

(EQ. 20)

IOC1x 80 10

–

RSETx

RSENx

------------------- A

 



(EQ. 21)

IOCNEGx

–

10 6

–

RSETx

RSENx

------------------- A

 



(EQ. 22)

IOC2x 105 10

–

RSETx

RSENx

------------------- A

 



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