68HC05PL4B datasheet(65/98 Pages) FREESCALE

65 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

8-BIT TIMER

REV 2.0

10-3

T8EN - Timer8 Enable

This read/write bit enables the Timer8. Reset clears this bit.

1 = Timer8 enabled

0 = Timer8 disabled

PS2-PS0 - Prescaler select

These read/write bits is used to select the clock frequency to drive the 8-bit timer

counter. The counter will be driven by a internal bus clock (E-clock) through this

prescaler ratio. Upon reset and power on reset, the value of prescaler is set to a

default value of divided by 16.

10.3

TIMER8 COUNTER REGISTER (T8CNTR)

The T8CNTR is a read/write register which contains the current value of the 8-bit

timer counter. Reading this register enables the software to calculate the number

of internal and external clocks since the timer interrupt request ag (T8IF) was

set. Reading this address does not disturb the counter operation.

NOTE

This timer is used during the power-on sequence to time out the POR signal. The

timer is con gured at po wer-on, with a prescaler division ratio of 16 and set to $FF

in Timer counter register. Also the clock source for the COP watchdog system is

derived from the output of this timer, hence a reset or preset of the prescaler and

timer counter register may affect the frequency of the watchdog timeout.

10.4

COMPUTER OPERATING PROPERLY (COP) WATCHDOG

Please refer to section on RESETS for details.

PS2

PS1

PS0

DIVIDE RATIO

000

001

010

011

16 (default after reset)

101

110

111

128

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

T8CNTR R

Timer 8 Counter Register

$000E

reset:

UUUUUUUU

Figure 10-3. Timer8 Counter Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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