68HC05PL4B datasheet(55/98 Pages) FREESCALE

55 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

16-BIT PROGRAMMABLE TIMER

REV 2.0

9-5

NOTE

To prevent interrupts from occurring between readings of the ACRH and ACRL,

set the I bit in the condition code register (CCR) before reading ACRH and clear

the I bit after reading ACRL.

9.3

INPUT CAPTURE REGISTERS

The input capture function is a technique whereby an external signal (connected

to PA2/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-

ble to relate the timing of an external signal to the internal counter value, and

hence to elapsed time.

When the input capture circuitry detects an active edge on the selected source, it

latches the contents of the free-running timer counter registers into the input cap-

ture registers as shown in Figure 9-6.

Latching values into the input capture registers at successive edges of the same

polarity measures the period of the selected input signal. Latching the counter val-

ues at successive edges of opposite polarity measures the pulse width of the sig-

nal.

Figure 9-6. Timer Input Capture Block Diagram

The input capture registers are made up of two 8-bit read-only registers (ICRH,

ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt

trigger to improve noise immunity. The edge that triggers the counter transfer is

de ned by the input edge bit (IEDG) in the TCR. Reset does not affect the con-

tents of the input capture registers.

ICRH ($0014)

16-BIT COUNTER

÷ 4

INTERNAL

(XTAL ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

INPUT CAPTURE (ICF)

RESET

CLOCK

INTERRUPT

ICRL ($0015)

TIMER STATUS REG.

$0012

$0013

INTERNAL

DATA

READ

ICRH

READ

ICRL

LATCH

BUS

EDGE

SELECT

& DETECT

LOGIC

TCAP

INTERNAL

DATA

BUS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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