68HC05PL4B datasheet(37/98 Pages) FREESCALE

37 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

RESETS

REV 2.0

5-5

5.4

RESET STATES OF SUBSYSTEM IN MCU

The following paragraphs describe how a reset initializes various sub-systems.

5.4.1 CPU

A reset has the following effects on the CPU:

•

Loads the stack pointer with $FF.

•

Sets the I bit in the condition code register, inhibiting interrupts.

•

Loads the program counter with the user de ned reset vector from

locations $1FFE and $1FFF.

•

Clears the stop latch, enabling the CPU clock.

•

Clears the wait latch, bringing the CPU out of the wait mode.

5.4.2 I/O Registers

A reset has the following effects on I/O registers:

•

Clears bits in data direction registers con gur ing pins as inputs:

– DDRA6–DDRA0 in DDRA for port A.

– DDRB7–DDRB0 in DDRB for port B.

– DDRC7–DDRC0 in DDRC for port C.

•

Has no effect on port A, B, C data registers.

5.4.3 8-Bit Timer

A reset has the following effects on the 8-Bit Timer:

•

Timer 8 system disabled (T8EN bit cleared)

•

Timer 8 interrupt request disabled

•

Timer 8 Pre-scalar preset to divide the internal bus clock by ratio 16

•

Timer 8 Counter register preset to $FF

Therefore disables the timer 8 interrupt and preset the counter for POR cycle

delay.

5.4.4 16-Bit Programmable Timer

A reset has the following effects on the 16-bit programmable Timer:

•

Initializes the timer counter registers (TMRH, TMRL) to a value of

$FFFC.

•

Initializes the alternate timer counter registers (ACRH, ACRL) to a value

of $FFFC.

•

Clears all the interrupt enables and the output level bit (OLVL) in the

timer control register (TCR).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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