68HC05PL4B datasheet(34/98 Pages) FREESCALE

34 / 98 page

GENERAL RELEASE SPECIFICATION

April 30, 1998

RESETS

MC68HC05PL4

5-2

REV 2.0

A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows

the clock generator to stabilize. If the RESET pin is at logic zero at the end of the

multiple tCYC time, the MCU remains in the reset condition until the signal on the

RESET pin goes to a logic one.

POR - Power on Reset Flag

The POR bit is set each time the device is powered on. It allows the user to

make a software distinction between a power-on and an external reset. POR

can be cleared by software by writing a ‘0’ to the bit. It cannot be set by soft-

ware.

5.2

EXTERNAL RESET

A logic zero applied to the RESET pin for 1.5tCYC generates an external reset.

This pin is connected to a Schmitt trigger input gate to provide an upper and lower

threshold voltage separated by a minimum amount of hysteresis. The external

reset occurs whenever the RESET pin is pulled below the lower threshold and

remains in reset until the RESET pin rises above the upper threshold. This active

low input will generate the internal RST signal that resets the CPU and peripher-

als.

The RESET pin can also act as an open drain output. It will be pulled to a low

state by an internal pulldown device that is activated by three internal reset

sources. This RESET pulldown device will only be asserted for 3-4 cycles of the

internal clock, fOP, or as long as the internal reset source is asserted. When the

external RESET pin is asserted, the pulldown device will not be turned on.

NOTE

Do not connect the RESET pin directly to VDD, as this may overload some power

supply designs when the internal pulldown on the RESET pin activates.

5.3

INTERNAL RESETS

The four internally generated resets are the initial power-on reset function, the

COP Watchdog timer reset, the low voltage reset, and the illegal address detector.

Only the COP Watchdog timer reset, low voltage reset and illegal address detec-

tor will also assert the pulldown device on the RESET pin for the duration of the

reset function or 3-4 internal clock cycles, whichever is longer.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MICSR R

IRQEN

IRQS

TCMPEN TCAPEN

LED

COPON

POR

$001C W

RESET

00000000

Figure 5-2. Miscellaneous Control and Status Register (MICSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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