ADuM1253

Ultra-Low-Power, I2C Isolator with

Unidirectional SCL, Extended VDD,

Idle-Bus Hot-Swap, and Low VOL

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Analog Devices | 20

The ADuM1253’s utputs are all pen-drain and require pull-up resistors to their respective supplies to generate the logic-

high output voltage. The output low voltages are guaranteed for sink currents of up to 50mA for side 2 and 5mA for side

1 (see the Electrical Characteristics table).

Startup and Undervoltage Lockout

The VDD1 and VDD2 supplies are both internally monitored for undervoltage conditions. Undervoltage events can occur

during power-up, power-down, or during normal operation due to a sagging supply voltage. When an undervoltage

condition is detected on either supply, all outputs go to their default states regardless of the state of the inputs as seen in

Table 1.

Table 1. Output Behavior During Undervoltage Condition

VDD1

VDD2

INPUT

VOUT1

VOUT2

Powered

Powered

High

High-Z

High-Z

Powered

Powered

Low

Low

Low

Undervoltage

Powered

n’t care

High-Z

High-Z

Powered

Undervoltage

n’t care

High-Z

High-Z

Level Shifting

The wide supply voltage range of both VDD1 and VDD2 allows the ADuM1253 to be used for level translation in addition

to isolation. VDD1 and VDD2 can be independently set to any voltage from 1.71V to 5.5V. The supply voltage sets the

logic level on the corresponding side of the isolator.

Hot Swap

The ADuM1253 includes special precharge circuitry on SDA2/SCL2 to prevent loading on the I2C bus lines while the

supply is either unpowered or in the process of being powered on. When the supply is below the UVLO threshold, the

ADuM1253 bus lines do not load the bus to avoid disrupting or corrupting an active I2C bus. If the isolator is plugged into

a live backplane using a staggered connector, where the supply and ground make connection first followed by the bus

lines, the SDA2 and SCL2 lines are precharged to VDD2/3 to minimize the current required to charge the parasitic

capacitance of the device. Once the device is fully powered on, the device I/O pins become active. However, the

connection between side 1 and side 2 does not occur until after the side 2 bus either detects an I2C stop condition or the

bus has been idle for 125µs. See Figure 7.