ADuM1253

Ultra-Low-Power, I2C Isolator with

Unidirectional SCL, Extended VDD,

Idle-Bus Hot-Swap, and Low VOL

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Analog Devices | 19

Functional Diagram

VDD1

SDA1

SCL1

GND1

VDD2

SDA2

SCL2

GND2

DECODE

ENCODE

ENCODE

DECODE

DECODE

ENCODE

1

2

3

4

8

7

6

5

Detailed Description

The ADuM1253 is a two-channel I2C isolator utilizing Analog Devices, Inc. proprietary process technology. The device

transfers digital signals between circuits with different power domains at ambient temperatures up to +125°C.

The device offers two open-drain channels, one bidirectional for data and one unidirectional for clock and is suitable for

I2C applications where only a single clock direction across the isolation barrier is required. Example applications include

I2C bus topologies where all I2C controllers are located on one side of the isolation barrier and/or where clock stretching

is not used by devices on the non-controller side of the isolation barrier.

The device features independent 1.71V to 5.5V supplies on each side of the isolator. The device operates with SCL

frequencies up to 2MHz. The wide temperature range and high isolation voltage make the device ideal for use in harsh

industrial environments.

Digital Isolation

The ADuM1253 provides reinforced galvanic isolation for digital signals that are transmitted between two ground domains.

In the 8-pin MSOP package (21-0036), the ADuM1253 withstands voltage differences of up to 2.5kVRMS for up to 60

seconds and up to 424VPEAK of continuous isolation.

In the 8-pin narrow SOIC package (21-0041), the ADuM1253 withstands voltage differences of up to 3kVRMS for up to

60 seconds and up to 630VPEAK of continuous isolation.

In the 8-pin wide SOIC package (21-100415), the ADuM1253 withstands voltage differences of up to 5kVRMS for up to

60 seconds and up to 1200VPEAK of continuous isolation.

Bidirectional Channels

The ADuM1253 device features one bidirectional channel which has open-drain outputs.

The bidirectional channels do not require a direction control input. A logic-low on one side causes the corresponding pin

on the other side to be pulled low while avoiding data latching within the device due to the coordination of the side 1 output

logic-low voltage (VOL1) and input logic-low threshold (VIL1). The side 1 outputs utilize special buffers that regulate VOL1

to approximately 0.64V while keeping VIL1 at least 50mV lower than VOL1. This difference prevents an output logic-low

on side 1 from being accepted as an input low and subsequently transmitted to side 2, thus, preventing a latching action.

SDA2 and SCL2 are conventional outputs that do not regulate the logic-low output voltage.

Due to their special nature, the side 1 SDA/SCL pins of different ADuM1253 devices cannot be connected together. This

restriction also includes pins on other devices which employ similar buffers or rise-time accelerators. The side 2 pins do

not have this restriction. Therefore, the side 2 pins of the ADuM1253 can be connected to each other or to any other

bi irecti nal buffer r level translat r’s pin, inclu ing the si e 1 pins f the ADuM1253.