TMP93CS41 datasheet(136/248 Pages) TOSHIBA

136 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-134

Bit symbol

CAP2T5

EQ5T5

CAP1IN

CAP12M1

CAP12M0

CLE

T4CLK1

T4CLK0

Read/Write

R/W

After reset

TFF5 invert trigger

0: Disable trigger

1: Enable trigger

Function

Inverted

when the

UC value is

latched to

CAP2

Inverted

when the

up counter

matches

TREG5

0: Software

capture

1: Don’t

care

Capture timing

00: Disable

INT4 occurs at rising

edge.

01: TI4 ↑

TI5 ↑

INT4 occurs at rising

edge.

10: TI4 ↑

TI4 ↓

INT4 occurs at falling

edge.

11: TFF1 ↑

TFF1 ↓

INT4 occurs at rising

edge.

1: UC4

clear

enable

Timer 4 source clock

00: TI4

01: φT1

10: φT4

11: φT16

Figure 3.9.4 16-Bit Timer Controller Register (T4MOD) (2/2)

Capture control

INT4 control

Capture disable

CAP1 at TI4 rise

CAP2 at TI5 rise

Interrupt occurs at the rising

edge of TI4 (INT4) input.

CAP1 at TI4 rise

CAP2 at TI4 fall

Interrupt occurs at the falling

edge of TI4 (INT4) input.

CAP1 at TFF1 rise

CAP2 at TFF1 fall

Interrupt occurs at the rising

edge of TI4 (INT4) input.

Capture timing of timer4

The up counter 4 value is loaded to CAP1

(Software capture)

Always read as “1”

Software capture

Trigger disable (Invert prohibition)

Trigger enable (Invert permission)

Timer flip-flop 5 (TFF5) invert trigger

CAP2T5: Inverted when the up counter value is latched to CAP2

EQ5T5: Inverted when the up counter matches TREG5

T4MOD

(0038H)

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