TMP92FD54AI datasheet(9/84 Pages) TOSHIBA

9 / 84 page

2006-01-27

92FD54AI-9

TMP92FD54AI

OPERATION

This section describes the basic components, functions and operation of TMP92FD54AI.

3.1 CPU

TMP92FD54AI contains an advanced high-speed 32-bit CPU (900/H1 CPU)

3.1.1

CPU Outline

900/H1 CPU is high-speed and high-performance CPU based on 900/H CPU. 900/H1 CPU has

expanded 32-bit internal data bus to process Instructions more quickly.

Outline of 900/H1 CPU are as follows:

900/H1 CPU

Width of CPU Address Bus

24-bit

Width of CPU Data Bus

32-bit

Internal Operating Frequency

16 to 20MHz (@fOSC=8 to 10MHz)

Minimum Bus Cycle (Internal RAM) 1-clock access (50ns@fOSC=10MHz)

Internal RAM

32-bit 1-clock access

Internal ROM

32-bit interleave 2-1-1-1-clock access

8/16-bit 2-clock access

PORT, INTC,

MEMC

Internal I/O

8/16-bit 5 to 6-clock access

SEI, SIO, WDT,

8-bit Timer,

16-bit Timer,

RTC, 10-bit ADC,

SBI, CAN

External Device

8-bit 2-clock access (can insert some waits)

Minimum Instruction

Execution Cycle

1-clock(50ns@fOSC=10MHz)

Conditional Jump

2-clock(100ns@fOSC=10MHz)

Instruction Queue Buffer

12-byte

Instruction Set

Compatible with TLCS-900, 900/H, 900/L,

900/L1 and 900/H2 (NORMAL, MIN, MAX and

LDX instruction is deleted)

Micro DMA

8-channels

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