TMP92FD54AI datasheet(83/84 Pages) TOSHIBA

83 / 84 page

TMP92FD54AI

2006-01-27

92FD54AI-83

6.2

Points to Note

(1) Watchdog timer

The watchdog timer starts operation immediately after a reset is released. When the

watchdog timer is not to be used, disable it.

(2) The stable time of the internal clock

When releasing the external reset using “built-in clock doubler” until the internal reset is

released, the requiring time to stabilize the circuit is automatically set. See section 3.1.2

“Reset Operation” for details. Also when releasing standby mode in STOP mode using an

interrupt until the internal circuit starts the operation, the stable time of the oscillator is

automatically input. See section 3.4 “Standby Function (3) STOP mode” for details.

(3) Undefined bit in the built-in I/O register

When reading the undefined bit in the built-in I/O register, the undefined value is output.

Thus, when creating program, it should not be depending on this bit condition.

(4) Reserved address areas

The 16 bytes area (FFFFF0H to FFFFFFH) cannot be used for it is reserved as internal

area. If using emulator, optional 64 Kbytes of 16M bytes area are used for control emulator.

Therefore, if using emulator, its area cannot be used.

(5) POP SR instruction

Execute the POP SR instruction during DI condition.

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