TMPR4937 datasheet(241/552 Pages) TOSHIBA

241 / 552 page

Chapter 9 SDRAM Controller

9-25

9.4.5

ECC Status Register (ECCSR)

0xA008

ERRAD

:Type

—

:Initial value

ERRAD

:Type

—

:Initial value

ERRAD

Reserved

ERRMODE

Reserved

ERRMW

Reserved

:Type

—

:Initial value

ERRS

Reserved

MBERR SBERR

R/W

R/W :Type

—

:Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:28

ERRAD

Error Address

Error Address (Default: Unknown)

A 36-bit physical address is set when an error occurs. This address is

retained until either SBERR or MBERR is cleared. This field is Read Only.

—

Reserved

⎯

26:24

ERRMODE

Error ECC/Parity

Mode

Error ECC Mode (Default: Unknown)

The ECC/Parity Mode is set when an error occurs. This address is retained

until either SBERR or MBERR is cleared. This field is Read Only.

23:22

—

Reserved

⎯

ERRMW

Error Memory

Width

Error Memory Width (Default: Unknown)

The memory data width is set when an error occurs. This address is

retained until either SBERR or MBERR is cleared. This field is Read Only.

0: 64 bits

1: 32 bits

20:16

—

Reserved

⎯

15:8

ERRS

Error Syndrome

Error Syndrome (Default: Unknown)

The error syndrome for when errors occur is set. The syndrome is retained

until either SBERR or MBERR is cleared. This field is Read Only.

7:2

—

Reserved

⎯

MBERR

Multi-Bit Error

Multi-Bit Error (Default: 0)

This bit is set to “1” when a multi-bit error occurs, or when a parity error

occurs while in the Parity Mode. Once a multi-bit error occurs, until this bit

is cleared, no status in the Status Register is updated even if new multi-

/single-bit errors occur.

0: No error

1: Generate error

R/W

SBERR

Single-Bit Error

Single-Bit Error (Default: 0)

This bit is set to “1” when a single-bit error occurs. Once a single-bit error

occurs, until this bit is cleared, no status in the Status Register is updated

even if new single-bit error occurs. If a multi-bit error occurs, status is

updated regardless of whether a single-bit error has occurred or not.

0: No error

1: Generate error

R/W

Figure 9.4.5 ECC Status Register

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