TMPR4937 datasheet(230/552 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-14

9.3.10.2 ECC Error Notification

When either an ECC error or a parity error occurs, error data is written into one of the following

fields, then error notification is performed as described below:

•

Error Address Field (ERRAD) in the ECC Status Register (ECCSR)

•

Error ECC/Parity Mode Field (ERRMODE)

•

Error Memory Width Field (ERRMW)

•

Error Syndrome Field (ERRS)

The Multi-bit Error bit (ECCSR.MBERR) of the ECC Status Register is set and an interrupt is

generated if either an ECC multi-bit error or parity error is detected during any Read/Write access

while the Multi-bit Error Interrupt Enable bit (ECCCR.MEI) is set.

The Single-bit Error bit (ECCSR.SBERR) of the ECC Status Register is set and an interrupt is

generated if an ECC single-bit error is detected during any Read/Write access while the Single-bit

Error Interrupt Enable bit (ECCCR.SEI) is set.

Multi-bit errors are assigned a higher priority than single-bit errors. If a multi-bit error is

detected while the Single-bit Error bit (ECCSR.SBERR) is set, then the Single-bit Error bit

(ECCSR.SBERR) is cleared, error data is written for the multi-bit error, then error notification is

performed. If a single-bit error is detected while the Multi-bit Error bit (ECCSR.MBERR) is set,

the Single-bit Error bit (ECCSR.SBERR) is not set and not error data is written. However, the

single-bit error is corrected according to the usual procedure.

The following error notification will also be performed if either an ECC multi-bit error or parity

error is detected while the Multi-bit Error Bus Error Enable Bit (ECCCR.MEB) of the ECC

Control Register is set.

During read access by the TX49 core, bus error notification is sent to the TX49 core and an

exception is generated. A nonmaskable interrupt is generated during Read-Modify-Write memory

Read access that is performed when writing from the TX49 core data that is smaller than 64 bits.

Bus error notification is sent to the appropriate bus master during Read/Write access from another

bus master.

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