TMPR4937 datasheet(124/552 Pages) TOSHIBA

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Chapter 7 External Bus Controller

7-24

7.5

Timing Diagrams

Please take the following points into account when referring to the timing diagrams.

(1) The clock frequency of the SYSCLK signal can be set to one of the following divisions of the internal

bus clock (GBUSCLK): 1/1, 1/2, 1/3, or 1/4. Also, the operating reference clock frequency can be set to

one of the following divisions of the internal bus clock (GBUSCLK) for each channel: 1/1, 1/2, 1/3, or

1/4. (See 7.3.8.) The timing diagrams indicate the SYSCLK signal clock frequency and channel

operating reference clock frequency as being equivalent.

(2) Both the BWE* signal and BE* signal are indicated in all timing diagrams. The setting of the Channel

Control Register (EBCCRn) determines whether the BWE* pin will function as BWE* or BE*.

(3) All Burst cycles in the timing diagrams illustrate examples in which the address increases by increments

of 1 starting from 0. However, cases where the CWF (Critical Word First) function of the TX49 core

was used or the decrement burst function performed by the DMA Controller was used are exceptions.

(4) The timing diagrams display each clock cycle currently being accessed using the symbols described in

the following table.

SWn

Normal Wait Cycles

PWn

Page Wait Cycles

ASn

Set-up Time from SHWT Address Validation to CE Fall

CSn

Set-up Time from SHWT CE Fall to OE/SWE Fall

AHn

Hold Time from SHWT CE Rise to Address Change

CHn

Hold Time from SHWT OE/SWE Rise to CE Rise

ESn

Synch Cycles of the External Input Signal

ACEn

Address Clock Enable Cycles

Other Cycles

(5) Shaded areas (

) in the diagrams are undefined values.

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