TMPR4937 datasheet(401/552 Pages) TOSHIBA

401 / 552 page

Chapter 12 Timer/Counter

12-17

12.4.8 Watchdog Timer Mode Register n (TMWTMRn)

TMWTMR2 0xF240

Reserved

: Type

: Initial value

TWIE

Reserved

WDIS

TWC

R/W

RW1S

R/W1C : Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:16

Reserved

⎯

TWIE

Watchdog Timer

Signaling Enable

Timer Watchdog Enable (Default: 0)

This bit sets NMI signaling enable/disable either when in the Watchdog

Timer mode or during a reset. This bit cannot be cleared when the

Watchdog Timer Disable bit (WDIS) is “0”.

0: Disable (mask)

1: Enable

R/W

14:8

Reserved

⎯

WDIS

Watchdog Timer

Disable

Watchdog Timer Disable (Default: 0)

Only when this bit is set can the counter be stopped by clearing the

Watchdog Timer Signaling Enable bit (TWIE) or by clearing the Timer

Counter Enable bit (TMTCR2.TCE) of the Timer Control Register.

Writing “0” to this bit is not valid. This bit can be cleared in either of the

following ways.

Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.TWIE).

Clear the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control

R/W1S

6:1

Reserved

⎯

TWC

Watchdog Timer

Clear

Watchdog Timer Clear (Default: 0)

Setting this bit to “1” clears the counter. Writing “0” to this bit is not valid.

This bit is always read as “0”.

R/W1C

Figure 12.4.8 Watchdog Timer Mode Register

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