TMPR4937 datasheet(381/552 Pages) TOSHIBA

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Chapter 11 Serial I/O Port

11-21

11.4.6 Flow Control Register 0 (SIFLCR0)

0xF314 (Ch. 0)

Flow Control Register 1 (SIFLCR1)

0xF414 (Ch. 1)

Reserved

: Type

: Initial value

Reserved

RCS

TES Reserved RTSSC RSDE TSDE

Reserved

RTSTL

TBRK

R/W

R/W : Type

0001

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:13

Reserved

⎯

RCS

RTS Signal

Control Select

RTS Control Select (Default: 0)

This field sets the reception flow control using RTS output signals.

0: Disable flow control using RTS signals.

1: Enable flow control using RTS signals.

R/W

TES

CTS Signal

Control Select

CTS Control Select (Default: 0)

This field sets the transmission flow control using CTS input signals.

0: Disable flow control using CTS signals.

1: Enable flow control using CTS signals.

R/W

Reserved

⎯

RTSSC

RTS Software

Control

RTS Software Control (Default: 0)

This register is used for software control of RTS output signals.

0: Set the RTS signal to Low (can receive data).

1: Sets the RTS signal to High (transmission pause request)

R/W

RSDE

Serial Data

Reception

Disable

Receive Serial Data Disable (Default: 1)

This is the Serial Data Disable bit. When this bit is cleared, data reception

starts after the start bit is detected. The RTS signal will not become High

even if this bit is cleared.

0: Enable (can receive data)

1: Disable (halt reception)

R/W

TSDE

Serial Data

Transmit Disable

Transmit Serial Data Disable (Default: 1)

This is the Serial Data Transmission Disable bit. When this bit is cleared,

data transmission starts. When set, transmission stops after completing

transmission of the current frame.

0: Enable (can transmit data)

1: Disable (halt transmission)

R/W

6:5

Reserved

⎯

4:1

RTSTL

RTS Active

Trigger Level

RTS Trigger Level (Default: 0001)

The RTS hardware control assert level is set by the reception data stage

count of the Receive FIFO.

0000: Disable setting

0001: 1

1111: 15

R/W

TBRK

Break

Transmission

Break Transmit (Default: 0)

Transmits a break. The TXD signal is Low while TBRK is set to “1”.

0: Disable (clear break)

1: Enable (transmit break)

R/W

Figure 11.4.6 Flow Control Register

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