M58PR256J datasheet(51/114 Pages) STMICROELECTRONICS

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M58PR256J, M58PR512J

Configuration Register

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7.3

Wait Polarity bit (CR10)

The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst

Read mode.

When:

●

CR10 = 0, the Wait signal is active Low,

●

CR10 = 1, the Wait signal is active High.

During Synchronous Burst Read mode the Wait signal indicates whether the data output are

valid or a WAIT state must be inserted.

7.4

Wait Configuration bit (CR8)

The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in

Synchronous Burst Read mode.

When:

●

CR8 = 0, the Wait output pin is asserted during the WAIT state,

●

CR8 = 1, the Wait output pin is asserted one data cycle before the WAIT state.

When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid.

7.5

Burst length bits (CR2-CR0)

The Burst Length bits are used to set the number of Words to be output during a

Synchronous Burst Read operation as result of a single address latch cycle.

They can be set for 8 Words, 16 Words or continuous burst, where all the Words are read

sequentially. In Continuous Burst mode the burst sequence can cross bank boundaries.

In Continuous Burst mode, the device asserts the WAIT signal to indicate that a delay is

necessary before the data is output.

In Continuous Burst mode, if the starting address is not aligned to the 16 Word boundary,

WAIT will be asserted when the burst sequence crosses the first 16 Word boundary to

indicate that the device needs an internal delay to read the successive Words in the array.

In the worst case, the number of WAIT states is one clock cycle less than the latency setting.

WAIT will be asserted only once during a continuous burst access. See also Table 16: Burst

type definition.

CR9, CR7, CR6, CR5, CR4 and CR3 are reserved for future use.

Table 14.

X-latency settings

fmax

tKmin

X-Latency

40 MHz

25 ns

54 MHz

19 ns

66 MHz

15 ns

108MHz

9ns

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