M58PR256J datasheet(21/114 Pages) STMICROELECTRONICS

21 / 114 page

M58PR256J, M58PR512J

Command interface

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4.1

Read Array command

The Read Array command returns the addressed bank to Read Array mode.

One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read

Array mode, subsequent read operations will output the data from the memory array.

A Read Array command can be issued to any banks while programming or erasing in

another bank.

If the Read Array command is issued to a bank currently executing a program or erase

operation, the bank will return to Read Array mode but the program or erase operation will

continue, however the data output from the bank is not guaranteed until the program or

erase operation has finished. The read modes of other banks are not affected.

4.2

Read Status Register command

The device contains a Status Register that is used to monitor program or erase operations.

The Read Status Register command is used to read the contents of the Status Register for

the addressed bank.

One Bus Write cycle is required to issue the Read Status Register command. Once a bank

is in Read Status Register mode, subsequent read operations will output the contents of the

Status Register.

The Status Register data is latched on the falling edge of the Chip Enable or Output Enable

signals. Either Chip Enable or Output Enable must be toggled to update the Status Register

data

The Read Status Register command can be issued at any time, even during program or

erase operations. The Read Status Register command will only change the read mode of

the addressed bank. The read modes of other banks are not affected. Only Asynchronous

Read and Single Synchronous Read operations should be used to read the Status Register.

A Read Array command is required to return the bank to Read Array mode.

See Table 13 for the description of the Status Register Bits.

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