M58PR256J datasheet(93/114 Pages) STMICROELECTRONICS

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M58PR256J, M58PR512J

Common Flash Interface

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Table 46.

Bank and Erase block region information

Offset(1)

The variable P is a pointer which is defined at CFI offset 015h.

Data

Description

(P+22)h = 12Ch

01h

Number of Bank Regions within the device(2)

Bank Regions. There is one Bank Region, see Tables 35, 36, 37 and 38 in Appendix A.

Table 47.

Bank and Erase block region 1 information(1)

Offset

Data

Description

(P+23)h = 12Dh

16h

Data size of this Bank Region Information Section (addressable locations

including this one)

(P+24)h = 12Eh

00h

(P+25)h = 12Fh

08h

Number of identical banks within Bank Region 1

(P+26)h = 130h

00h

(P+27)h = 131h

11h

Number of program or erase operations allowed in Bank Region 1:

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+28)h = 132h

00h

Number of program or erase operations allowed in other banks while a

bank in this region is being erased

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+29)h = 133h

00h

Number of program or erase operations allowed in other banks while a

bank in this region is being erased

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2A)h = 134h

01h

Types of erase block regions in Bank Region 1

n = number of erase block regions with contiguous same-size erase

blocks.

Symmetrically blocked banks have one blocking region(2)

(P+2B)h = 135h

0Fh(3)

1Fh(4)

Bank Region 1 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks in each bank

Bits 16-31: n×256 = number of bytes in erase block region

(P+2C)h = 136h

00h

(P+2D)h = 137h

00h

(P+2E)h = 138h

04h

(P+2F)h = 139h

64h

Bank Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000

(P+30)h = 13Ah

00h

(P+31)h = 13Bh

12h

Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

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