M58PR256J datasheet(33/114 Pages) STMICROELECTRONICS

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M58PR256J, M58PR512J

Command interface

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4.23

Program EFA Block command

The Program EFA Block command is used to program a single Word to an EFA Block.

Two Bus Write cycles are required to issue the Program EFA Block command.

●

The first bus cycle sets up the Program EFA Block command.

●

The second cycle latches the address and data to be programmed and starts the

Program/Erase Controller.

Once the programming has started, read operations in the bank being programmed output

the Status Register contents.

Issuing the Program EFA Block command to an address outside the EFA Block address

range generates a Program Error in the Status Register (SR4=1)

A Read EFA Block command is required to return the bank to Read EFA mode. Refer to

Section 11: Dual operations and multiple bank architecture for detailed information about

simultaneous operations allowed in the banks not being programmed. Typical EFA Program

times are given in Table 22: Program/Erase times and endurance cycles.

The Program operation aborts if Reset, RP, is at VIL. As data integrity cannot be guaranteed

when a Program EFA Block operation is aborted, the Word must be reprogrammed. See

Appendix C, Figure 20: Program and EFA Block Program flowchart and pseudo code, for

the flowchart for using the Program EFA Block command.

4.24

Erase EFA Block command

The Erase EFA Block command is used to erase an EFA Block. It sets all the bits within the

selected Block to '1'. All previous data in the Block is lost. If the EFA Block is protected then

the erase operation will abort, the data in the EFA Block will not be changed and the Status

Two Bus Write cycles are required to issue the command.

●

The first bus cycle sets up the Erase EFA Block command.

●

The second latches the EFA Block address and starts the Program/Erase Controller.

The first cycle brings the EFA plane to the foreground and latches the address of the EFA

Block to be erased. Reading from the bank when the EFA plane is in the foreground returns

the Status Register.

Once the erase operation has started, read operations in the bank being erased output the

Status Register contents.

If the Erase EFA Block Confirm command code is not issued in the second bus cycle, Status

remains in the Read Status Register mode.

Issuing the Erase EFA Block command outside the EFA Block address range generates an

error in the Status Register (SR5=1).

The Erase EFA Block operation will abort if Reset, RP, is at VIL. As data integrity cannot be

guaranteed when the Erase EFA Block operation is aborted, the Block must be erased

again.

Refer to Section 11: Dual operations and multiple bank architecture section for detailed

information about simultaneous operations allowed with array and non-array Blocks. Typical

Erase times are given in Table 22: Program/Erase times and endurance cycles.

See Appendix C, Figure 23: Block Erase and EFA Block Erase flowchart and pseudo code,

for a suggested flowchart for using the Erase EFA Block command.

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