TAS5815PWPR datasheet(46/123 Pages) TI

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7.5.2.4 Sequential Read

A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are

transmitted by the device to the master device as shown in Figure 7-13. Except for the last data byte, the master

device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C

sub address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed

by a stop condition to complete the transfer.

Not

Acknowledge

Repeat Start

Condition

Acknowledge

Start

Condition

2C Device Address

and R/W Bit

Subaddress

2C Device Address

and R/W Bit

First Data Byte

Other Data Byte

Last Data Byte

Stop

Condition

ACK

D0 ACK D7

ACK

R/W

ACK

A0 ACK

R/W ACK

Figure 7-13. Sequential Read Transfer

7.5.2.5 DSP Memory Book, Page and BQ update

The TAS5815 device supports the I2C serial bus and the data transmission protocol for standard and fast mode

as a target device.

The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has

several registers.

Because the TAS5815 register map spans several books and pages, the user must select the correct book and

page before writing individual register bits or bytes.

To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.

On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to

change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book

number to register 0x7f on page 0. To change between pages in a book, simply write the page number to

All the Biquad Filters coefficients are addressed in Book 0xAA. The five coefficients of every Biquad Filter should

be written entirely and sequentially from the lowest address to the highest.

7.5.2.6 Example Use

The following is a sample script for configuring a device on I2C target address 0xA8 and set the device switching

frequency to 768kHz with Class D loop bandwidth to 175kHz, BD Modulation:

• w A8 00 00 #Go to Page0

• w A8 7f 00 #Change the Book to 0x00

• w A8 00 00 #Go to Page 0x00

• w A8 02 01 #Set switching frequency to 768kHz with 1SPW Modulation

• w A8 53 60 #Set Class D Loop Bandwidth to 175kHz

Example 2, The following is a sample script for configuring a device on I2C target address 0xA8 and using the

DSP host memory to change the digital volume to the default value of 0dB:

• w A8 00 00 #Go to Page 0

• w A8 7f 8c #Change the Book to 0x8C

• w A8 00 2a #Go to Page 0x2a

• w A8 24 00 80 00 00 #change digital volume to 0 dB

7.5.2.7 Checksum

This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an

Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers

will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.

TAS5815

SLOSEA8 – DECEMBER 2024

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